CREATE AND SAMPLE YOUR CUSTOM PL613 HERE
The PL613-21 is an advanced three PLL design based on PicoPLL, the world’s smallest programmable clock technology. This advanced technology allows the PL613-21 to fit in to a small 3mm x 3mm QFN package for high performance, low-power, small form-factor applications. By using the individual output buffer VDD pins, the PL613-21 can support multiple output voltage requirements. In addition, CLK1 has the ability to generate kHz outputs and is ideal for generating 32.768kHz outputs.The unique power down features of the PL613-21 allows the user to shut down individual PLLs when the corresponding clock output is disabled using the PDB pins. The output drive strength can be individually programmed on each output to Low (4mA), Standard (8mA) or High (16mA) drive. In addition, the disabled state of the clock outputs can be programmed as Hi-Z or Active Low.Besides its small form factor and multiple outputs that can reduce overall system costs, the PL613-21 offers superior phase noise, jitter and power consumption performance.
Additional Features
Designed for PCB space savings with 3 low-power Programmable PLLs
Ultra Low-Power Consumption
Ultra-Low Power Down Mode, <5µA Typical
CLK1 Capable of Generating 32.768kHz
Individual Output Buffer VDD Pins for Flexible Output Voltages, 1.8V to 3.3V ±10%
Individual PLL Power Down Control
Output Frequency (based on VDD_CORE voltage):
≤65MHz @ 1.8V operation
≤90MHz @ 2.5V operation
≤125MHz @ 3.3V operation
Input Frequency:
Fundamental Crystal: 10MHz to 40MHz
Reference Input: 10MHz to 200MHz
Active Low or Hi-Z Disabled Output State
1.8V to 3.3V ±10% Core Power Supply
1.8V to 3.3V ±10% Buffer Power Supply
Temperature range:
0°C to +70°C
-40°C to +85°C
Available in GREEN/RoHS compliant 3mm x 3mm QFN package
CREATE AND SAMPLE YOUR CUSTOM PL613 HERE
The PL613-21 is an advanced three PLL design based on PicoPLL, the world’s smallest programmable clock technology. This advanced technology allows the PL613-21 to fit in to a small 3mm x 3mm QFN package for high performance, low-power, small form-factor applications. By using the individual output buffer VDD pins, the PL613-21 can support multiple output voltage requirements. In addition, CLK1 has the ability to generate kHz outputs and is ideal for generating 32.768kHz outputs.The unique power down features of the PL613-21 allows the user to shut down individual PLLs when the corresponding clock output is disabled using the PDB pins. The output drive strength can be individually programmed on each output to Low (4mA), Standard (8mA) or High (16mA) drive. In addition, the disabled state of the clock outputs can be programmed as Hi-Z or Active Low.Besides its small form factor and multiple outputs that can reduce overall system costs, the PL613-21 offers superior phase noise, jitter and power consumption performance.
Additional Features
- Designed for PCB space savings with 3 low-power Programmable PLLs
- Ultra Low-Power Consumption
- Ultra-Low Power Down Mode, <5µA Typical
- CLK1 Capable of Generating 32.768kHz
- Individual Output Buffer VDD Pins for Flexible Output Voltages, 1.8V to 3.3V ±10%
- Individual PLL Power Down Control
- Output Frequency (based on VDD_CORE voltage):
- ≤65MHz @ 1.8V operation
- ≤90MHz @ 2.5V operation
- ≤125MHz @ 3.3V operation
- Input Frequency:
- Fundamental Crystal: 10MHz to 40MHz
- Reference Input: 10MHz to 200MHz
- Active Low or Hi-Z Disabled Output State
- 1.8V to 3.3V ±10% Core Power Supply
- 1.8V to 3.3V ±10% Buffer Power Supply
- Temperature range:
- 0°C to +70°C
- -40°C to +85°C
- Available in GREEN/RoHS compliant 3mm x 3mm QFN package
