The MEC1723 is an embedded controller designed for low power applications in notebook PCs and storage enclosure platforms. It features a 32-bit ARM® Cortex-M4F processor with a maximum clock frequency of 48 MHz and includes 416KB of SRAM, with 352KB optimized for code performance and 64KB for data performance. The device supports dual voltage operation at 1.8V and 3.3V, allowing compatibility with both modern and legacy systems. The MEC1723 incorporates an Intel® Enhanced Serial Peripheral Interface (eSPI) for communication, supporting multiple channels and modes. It includes advanced security features such as a secure bootloader, AES-256 encryption, and a True Random Number Generator (TRNG). The controller is designed to operate in various ACPI power states, with low power modes that enhance energy efficiency during operation and sleep states. Additionally, the MEC1723 provides a range of peripheral interfaces, including multiple I2C/SMBus controllers, UARTs, and GPIO pins, making it suitable for diverse applications requiring flexible I/O configurations. The device is packaged in a 144-pin WFBGA format, facilitating integration into compact designs.
The MEC1723 is a low power integrated embedded controller designed for notebook applications storage enclosure platforms. The MEC1723 is a highly-configurable,
When VTR_CORE is applied to the device, the secure bootloader API is used to download the custom firmware image from the system’s shared SPI Flash device, thereby allowing system designers to customize the device’s behavior. The MEC1723 device is directly powered by a minimum of two separate suspend supply planes (VBAT and VTR) and senses a third runtime power plane (VCC) to provide “instant on” and system power management functions. The MEC1723 has two banks of I/O pins that are able to operate at either 3.3 V or 1.8 V. Operating at 1.8V allows the MEC1723 to interface with the latest platform controller hubs and will lower the overall power consumed by the device, Whereas 3.3V allows this device to be integrated into legacy platforms that require 3.3V operation.
The MEC1723 host interface is the Intel® Enhanced Serial Peripheral Interface (eSPI). The eSPI Interface is a 1.8V interface that operates in single, double and quad I/O modes. The eSPI Interface supports all four eSPI channels: Peripheral Channel, Virtual Wires Channel, OOB Message Channel, and Run-time Flash Access Channel. The eSPI hardware Flash Access Channel is used by the Boot ROM to support Master Attached Flash Sharing (MAFS). In addition, the MEC1723 has specially designed hardware to support Slave Attached Flash Sharing (SAFS). The eSPI SAFS Bridge imposes Region-Based Protection and Locking security feature, which limits access to certain regions of the flash to specific masters. There may be one or more masters (e.g., BIOS, ME, etc) that will access the SAF via the eSPI interface. The ARM® Cortex-M4F processor is also considered a master, which will also have its access limited to EC only regions of SPI Flash as determined by the customer firmware application.The MEC1723 secure bootloader authenticates and optionally decrypts the SPI Flash OEM boot image using the AES-256, ECDSA, SHA-512 cryptographic hardware accelerators. The MEC1723 hardware accelerators support 128-bit and 256-bit AES encryption, ECDSA and EC_KCDSA signing algorithms, 1024-bits to 4096-bits RSA and Elliptic asymmetric public key algorithms, and a True Random Number Generator (TRNG). Runtime APIs are provided in the ROM for customer application code to use the cryptographic hardware. Additionally, the device offers lockable OTP storage for private keys and IDs.
The MEC1723 is designed to be incorporated into low power PC architecture designs and supports ACPI sleep states (S0-S5). During normal operation, the hardware always operates in the lowest power state for a given configuration. The chip power management logic offers two low power states: light sleep and heavy sleep. These features can be used to support S0 Connected Standby state and the lower ACPI S3-S5 system sleep states. In connected standby, any eSPI command will wake the device and be processed. When the chip is sleeping, it has many wake events that can be configured to return the device to normal operation. Some examples of supported wake events are PS2 wake events, RTC, Week Alarm, Hibernation Timer, or any GPIO pin.
The MEC1723 offers a software development system interface that includes a Trace FIFO Debug port, a host accessible serial debug port with a 16C550A register interface, a Port 80 BIOS Debug Port, and a 2-pin Serial Wire Debug (SWD) interface. Also included is a 4-wire JTAG interface used for Boundary Scan testing.
| Microchip Technology, Inc. | |
|---|---|
| Product Category | Memory Chips |
| Product Number | MEC1723 |
| Product Name | Embedded Controller with 2KB EEPROM |
| Memory Category | EEPROM |
