Microchip's cost-effective, software-programmabl
e solution is the Le58QL02/021/031 QLSLAC and the Le58QL061/063 QLSLAC line of DSP-based voice codec/filters. The four-channel QLSLAC devices handle the analog-to-digital and digital-to-analog conversion, filtering, compression and expansion functions required to interface a telephone's analog voice signals to the digital PCM highway or General Circuit Interface (GCI).
Additional Features
Low-power, 3.3 V CMOS technology with 5-V tolerant digital inputs
Software and coefficient compatible to the Le79Q02/ 021/031 QSLAC device
Performs the functions of four codec/filters
Software programmable
SLIC device input impedance
Transhybrid balance
Transmit and receive gains
Equalization (frequency response)
Digital I/O pins
Programmable debouncing on one input
Time slot assigner
Programmable clock slot and PCM transmit clock edge options
Standard microprocessor interface
A-law, µ-law, or linear coding
Single or Dual PCM ports available
Up to 128 channels (PCLK at 8.192 MHz) per PCM port
Optional supervision on the PCM highway
1.536, 1.544, 2.048, 3.072, 3.088, 4.096, 6.144, 6.176, or 8.192 MHz master clock derived from MCLK or PCLK
Built-in test modes with loopback, tone generation, and µP access to PCM data
Mixed state (analog and digital) impedance scaling
Performance guaranteed over a 12 dB gain range
Real Time Data register with interrupt (open drain or TTL output)
Supports multiplexed SLIC device outputs
Broadcast state
56 kHz or 293 kHz chopper clock for SLIC devices with switching regulator
Maximum channel bandwidth for V.90 modems
Microchip's cost-effective, software-programmable solution is the Le58QL02/021/031 QLSLAC and the Le58QL061/063 QLSLAC line of DSP-based voice codec/filters. The four-channel QLSLAC devices handle the analog-to-digital and digital-to-analog conversion, filtering, compression and expansion functions required to interface a telephone's analog voice signals to the digital PCM highway or General Circuit Interface (GCI).
Additional Features
- Low-power, 3.3 V CMOS technology with 5-V tolerant digital inputs
- Software and coefficient compatible to the Le79Q02/ 021/031 QSLAC device
- Performs the functions of four codec/filters
- Software programmable
- SLIC device input impedance
- Transhybrid balance
- Transmit and receive gains
- Equalization (frequency response)
- Digital I/O pins
- Programmable debouncing on one input
- Time slot assigner
- Programmable clock slot and PCM transmit clock edge options
- Standard microprocessor interface
- A-law, µ-law, or linear coding
- Single or Dual PCM ports available
- Up to 128 channels (PCLK at 8.192 MHz) per PCM port
- Optional supervision on the PCM highway
- 1.536, 1.544, 2.048, 3.072, 3.088, 4.096, 6.144, 6.176, or 8.192 MHz master clock derived from MCLK or PCLK
- Built-in test modes with loopback, tone generation, and µP access to PCM data
- Mixed state (analog and digital) impedance scaling
- Performance guaranteed over a 12 dB gain range
- Real Time Data register with interrupt (open drain or TTL output)
- Supports multiplexed SLIC device outputs
- Broadcast state
- 56 kHz or 293 kHz chopper clock for SLIC devices with switching regulator
- Maximum channel bandwidth for V.90 modems
