Microchip Technology, Inc. 10 Base-T Ethernet Controller LAN91C96

The LAN91C96 is a VLSI Ethernet Controller that combines Local Bus, PCMCIA, and Motorola 68000 bus interfaces in one chip. LAN91C96 integrates all MAC and physical layer functions, as well as the packet RAM, needed to implement a high performance 10BASE-T (twisted pair) node. For 10BASE5 (thick coax), 10BASE2 (thin coax), and 10BASE-F (fiber) implementations, the LAN91C96 interfaces to external transceivers via the provided AUI port. Only one additional IC is required for most applications. The LAN91C96 comes with Full Duplex Switched Ethernet (FDSWE) support allowing the controller to provide much higher throughput. 6K bytes of RAM is provided to support enhanced throughput and compensate for any increased system service latencies. The controller implements multiple advanced power-down modes including Magic Packet to conserve power and operate more efficiently. The LAN91C96 can directly interface with the Local Bus, PCMCIA, and 68000 buses and deliver no-wait-state operation. *The LANCheck online design review service is subject to Microchip's Program Terms and Conditions and requires a myMicrochip account. Additional Features Non-PCI Single-Chip Ethernet Controller A Subset of Motorola 6800 Bus Interface Support Fully Supports Full Duplex Switched Ethernet Supports Enhanced Transmit Queue Management 6K Bytes of On-Chip RAM Supports IEEE 802.3 (ANSI 8802-3) Ethernet Standards Automatic Detection of TX/RX Polarity Reversal Enhanced Power Management Features Supports "Magic Packet" Power Management Technology Hardware Memory Management Unit Optional Configuration via Serial EEPROM Interface (Jumperless) Supports Single +5V or +3.3V (for Revisions E and Later) VCC Design Supports Mixed Voltage External PHY Designs Low Power CMOS Design 100 Pin QFP and TQFP (1.0mm Body Thickness) RoHS Compliant Packages Pin Compatible with the LAN91C92 and LAN91C94 Direct Interface to Local Bus, PCMCIA, and 68000 Buses with No Wait States Flexible Bus Interface 16 Bit Data and Control Paths Fast Access Time Pipelined Data Path Handles Block Word Transfers for Any Alignment High Performance Chained ("Back-to-Back") Transmit and Receive Pin Compatible with the LAN91C92 (in Local Bus Mode) and the LAN91C94 in Both Local Bus and PCMCIA Modes Dynamic Memory Allocation Between Transmit and Receive Flat Memory Structure for Low CPU Overhead Buffered Architecture, Insensitive to Bus Latencies (No Overruns/Underruns) Supports Boot PROM for Diskless Local Bus Applications Driver and Receiver Link Integrity Test Receive Polarity Detection and Correction Integrated AUI Interface 10 Mb/s Manchester Encoding/Decoding and Clock Recovery Automatic Retransmission, Bad Packet Rejection, and Transmit Padding External and Internal Loopback Modes Four Direct Driven LED Outputs for Status/Diagnostics LAN9000 Drivers for Major Network Operating Systems Utilizing Local Bus or PCMCIA Interface Software Drivers Compatible with the LAN91C92, LAN91C94, LAN91C100FD (100 Mb/s), and LAN91C110 (100 Mb/s) Controllers in Local Bus Mode Software Drivers Utilize Full Capability of 32 Bit Microprocessor