The SST39VF6401B device is a 4M x16, CMOS Multi-Purpose Flash Plus (MPF+) manufactured with SST proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39VF6401B writes (Program or Erase) with a 2.7-3.6V power supply. This devices conforms to JEDEC standard pinouts for x16 memories and is command set compatible with Flash devices that support the AMD/Spansion command set, enabling customers to save time and resources in implementation.
Additional Features
Organized as 4M x16
Single Voltage Read and Write Operations– 2.7-3.6V
Superior Reliability– Endurance: 100,000 Cycles (Typical)– Greater than 100 years Data Retention
Low Power Consumption (typical values at 5 MHz)– Active Current: 9 mA (typical)– Standby Current: 3 µA (typical)– Auto Low Power Mode: 3 µA (typical)
Hardware Block-Protection/WP# Input Pin– Top Block-Protection (top 32 KWord)for SST39VF6402B– Bottom Block-Protection (bottom 32 KWord)for SST39VF6401B
Sector-Erase Capability– Uniform 2 KWord sectors
Block-Erase Capability– Uniform 32 KWord blocks
Chip-Erase Capability
Erase-Suspend/Erase-
Resume Capabilities
Hardware Reset Pin (RST#)
Security-ID Feature– SST: 128 bits; User: 128 bits
Fast Read Access Time:– 70 ns– 90 ns
Latched Address and Data
Fast Erase and Word-Program:– Sector-Erase Time: 18 ms (typical)– Block-Erase Time: 18 ms (typical)– Chip-Erase Time: 40 ms (typical)– Word-Program Time: 7 µs (typical)
Automatic Write Timing– Internal VPP Generation
End-of-Write Detection– Toggle Bits– Data# Polling
CMOS I/O Compatibility
JEDEC Standard– Flash EEPROM Pin Assignments– Software command sequence compatibility- Address format is 11 bits, A10-A0- Block-Erase 6th Bus Write Cycle is 30H- Sector-Erase 6th Bus Write Cycle is 50H
Packages Available– 48-lead TSOP (12mm x 20mm)– 48-ball TFBGA (8mm x 10mm)
All non-Pb (lead-free) devices are RoHS compliant
The SST39VF6401B device is a 4M x16, CMOS Multi-Purpose Flash Plus (MPF+) manufactured with SST proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39VF6401B writes (Program or Erase) with a 2.7-3.6V power supply. This devices conforms to JEDEC standard pinouts for x16 memories and is command set compatible with Flash devices that support the AMD/Spansion command set, enabling customers to save time and resources in implementation.
Additional Features
- Organized as 4M x16
- Single Voltage Read and Write Operations– 2.7-3.6V
- Superior Reliability– Endurance: 100,000 Cycles (Typical)– Greater than 100 years Data Retention
- Low Power Consumption (typical values at 5 MHz)– Active Current: 9 mA (typical)– Standby Current: 3 µA (typical)– Auto Low Power Mode: 3 µA (typical)
- Hardware Block-Protection/WP# Input Pin– Top Block-Protection (top 32 KWord)for SST39VF6402B– Bottom Block-Protection (bottom 32 KWord)for SST39VF6401B
- Sector-Erase Capability– Uniform 2 KWord sectors
- Block-Erase Capability– Uniform 32 KWord blocks
- Chip-Erase Capability
- Erase-Suspend/Erase-Resume Capabilities
- Hardware Reset Pin (RST#)
- Security-ID Feature– SST: 128 bits; User: 128 bits
- Fast Read Access Time:– 70 ns– 90 ns
- Latched Address and Data
- Fast Erase and Word-Program:– Sector-Erase Time: 18 ms (typical)– Block-Erase Time: 18 ms (typical)– Chip-Erase Time: 40 ms (typical)– Word-Program Time: 7 µs (typical)
- Automatic Write Timing– Internal VPP Generation
- End-of-Write Detection– Toggle Bits– Data# Polling
- CMOS I/O Compatibility
- JEDEC Standard– Flash EEPROM Pin Assignments– Software command sequence compatibility- Address format is 11 bits, A10-A0- Block-Erase 6th Bus Write Cycle is 30H- Sector-Erase 6th Bus Write Cycle is 50H
- Packages Available– 48-lead TSOP (12mm x 20mm)– 48-ball TFBGA (8mm x 10mm)
- All non-Pb (lead-free) devices are RoHS compliant
