A high-performance, high-density, complex programmable logic device (CPLD) that uses Atmel's proven electrically-erasabl
e memory technology. With 128 logic macrocells and up to 84 inputs, it easily integrates logic from several TTL, SSI, MSI, LSI and classic PLDs. Enhanced routing switch matrices increase usable gate count and the odds of successful pin-locked design modifications.
A high-performance, high-density, complex programmable logic device (CPLD) that uses Atmel's proven electrically-erasable memory technology. With 128 logic macrocells and up to 84 inputs, it easily integrates logic from several TTL, SSI, MSI, LSI and classic PLDs. Enhanced routing switch matrices increase usable gate count and the odds of successful pin-locked design modifications.
