Microchip Technology, Inc. AT91SAM9G46

Description
The Microchip's ARM®-based SAM9G46 is a 400MHz ARM926-based embedded microprocessor with hardware encryption, DDR2 and LPDDR support, wide range of connectivity and user interface peripherals, and dual external bus interface. The multi-layer bus architecture associated with 35 DMA channel and 64KB of SRAM can be configured as TCM, and the dual bus interface sustains the high bandwidth required by the processor and its high-speed peripherals. The hardware encryption engine features AES 256-, 192-, 128-bit key algorithms compliant with FIPS PUB 197 Specifications, TDES two-key or three-key algorithms compliant with FIPS PUB 46-3 Specifications, a SHA Secure Hash Algorithm (SHA1 and SHA256) compliant with FIPS Publication 180-2 and a TRNG compliant with NIST SP800-22 and Diehard Random Tests suite. It integrates multiple communication interfaces such as High Speed USB host and device with transceivers, 10/100 Mbps Ethernet controller and high-speed SDIO/MMC interface. It also comes with an LCD controller supporting up to 1280x860 resolution, a resistive touchscreen controller and a camera interface. The I/Os support 3.3V. The SAM9G46 is available in a BGA324 package with 0.8mm ball pitch.
Datasheet
Description
The Microchip's ARM®-based SAM9G46 is a 400MHz ARM926-based embedded microprocessor with hardware encryption, DDR2 and LPDDR support, wide range of connectivity and user interface peripherals, and dual external bus interface. The multi-layer bus architecture associated with 35 DMA channel and 64KB of SRAM can be configured as TCM, and the dual bus interface sustains the high bandwidth required by the processor and its high-speed peripherals. The hardware encryption engine features AES 256-, 192-, 128-bit key algorithms compliant with FIPS PUB 197 Specifications, TDES two-key or three-key algorithms compliant with FIPS PUB 46-3 Specifications, a SHA Secure Hash Algorithm (SHA1 and SHA256) compliant with FIPS Publication 180-2 and a TRNG compliant with NIST SP800-22 and Diehard Random Tests suite. It integrates multiple communication interfaces such as High Speed USB host and device with transceivers, 10/100 Mbps Ethernet controller and high-speed SDIO/MMC interface. It also comes with an LCD controller supporting up to 1280x860 resolution, a resistive touchscreen controller and a camera interface. The I/Os support 3.3V. The SAM9G46 is available in a BGA324 package with 0.8mm ball pitch.
Datasheet

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The Microchip's ARM®-based SAM9G46 is a 400MHz ARM926-based embedded microprocessor with hardware encryption, DDR2 and LPDDR support, wide range of connectivity and user interface peripherals, and dual external bus interface. The multi-layer bus architecture associated with 35 DMA channel and 64KB of SRAM can be configured as TCM, and the dual bus interface sustains the high bandwidth required by the processor and its high-speed peripherals. The hardware encryption engine features AES 256-, 192-, 128-bit key algorithms compliant with FIPS PUB 197 Specifications, TDES two-key or three-key algorithms compliant with FIPS PUB 46-3 Specifications, a SHA Secure Hash Algorithm (SHA1 and SHA256) compliant with FIPS Publication 180-2 and a TRNG compliant with NIST SP800-22 and Diehard Random Tests suite. It integrates multiple communication interfaces such as High Speed USB host and device with transceivers, 10/100 Mbps Ethernet controller and high-speed SDIO/MMC interface. It also comes with an LCD controller supporting up to 1280x860 resolution, a resistive touchscreen controller and a camera interface. The I/Os support 3.3V. The SAM9G46 is available in a BGA324 package with 0.8mm ball pitch.

The Microchip's ARM®-based SAM9G46 is a 400MHz ARM926-based embedded microprocessor with hardware encryption, DDR2 and LPDDR support, wide range of connectivity and user interface peripherals, and dual external bus interface. The multi-layer bus architecture associated with 35 DMA channel and 64KB of SRAM can be configured as TCM, and the dual bus interface sustains the high bandwidth required by the processor and its high-speed peripherals. The hardware encryption engine features AES 256-, 192-, 128-bit key algorithms compliant with FIPS PUB 197 Specifications, TDES two-key or three-key algorithms compliant with FIPS PUB 46-3 Specifications, a SHA Secure Hash Algorithm (SHA1 and SHA256) compliant with FIPS Publication 180-2 and a TRNG compliant with NIST SP800-22 and Diehard Random Tests suite. It integrates multiple communication interfaces such as High Speed USB host and device with transceivers, 10/100 Mbps Ethernet controller and high-speed SDIO/MMC interface. It also comes with an LCD controller supporting up to 1280x860 resolution, a resistive touchscreen controller and a camera interface. The I/Os support 3.3V. The SAM9G46 is available in a BGA324 package with 0.8mm ball pitch.

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Technical Specifications

  Microchip Technology, Inc.
Product Category Microprocessor Chips (MPU)
Product Number AT91SAM9G46
Microprocessor Family ARM
Supply Voltage 0.9 to 1.1
Package Type Other; ['TFBGA']
Pin Count 324
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