Linear Systems JFETs SST406 SOIC 8L-TB

The SST/U401 to SST/U406 are monolithic dual N-channel JFET amplifiers designed for low noise and low drift applications. The SOIC package variant features an 8-lead surface mount configuration. Each transistor supports a maximum gate-to-source voltage of -50V and a maximum power dissipation of 300mW at 25°C. Key electrical characteristics include a typical transconductance of 1000 µS at 200µA drain current, a pinch-off voltage of -2.5V maximum, and a gate-to-gate breakdown voltage of ±50V. Drain-source saturation current ranges from 0.5 to 10mA. Voltage drift between matched transistors is specified up to 80µV/°C for the U406. Input voltage noise is 6nV/Hz at 10Hz typical. The device operates over a junction temperature range of -55°C to +150°C and meets no specified industry standards. The SOIC-8 package dimensions are detailed but not summarized here.