The 10500/10100 series of emitter-coupled logic is the fastest logic technology available for practical use. A conventional planar process is used for the 10K ECL series with a density of about ten gates per mm2 and a delay of 2 ns per gate.
| Lansdale Semiconductor, Inc. | |
|---|---|
| Product Category | Parity Checkers and Generators |
| Product Number | 10560/E,F |
| Product Name | 12-Bit Parity Checker / Generator |
| Number of Bits | 12 |
| Supply Voltage | Other; (-8) VDC |
| Package Type | DIP (optional feature); Other (optional feature); Lead Flat Pack |
| Logic Family | ECL |
