InterFET Corporation JFET J177

P-channel silicon junction field-effect transistor for chopper, commutator, and analog switch applications in a TO-226AA surface-mount package. Maximum reverse gate-source and gate-drain voltage is 30 V, with continuous forward gate current of 50 mA and power dissipation of 360 mW at 25°C, derating at 3.27 mW/°C. Gate-source cutoff voltage ranges from 0.8 V to 2.25 V, and drain saturation current ranges from −1.5 mA to −20 mA at V_DS = −15 V. Drain-source ON resistance is 250 Ω to 300 Ω. Drain-gate and source-gate capacitance are each 5.5 pF. Turn-on and turn-off delay times are 15 to 20 ns, with rise and fall times of 20 to 25 ns. Pin configuration is drain (1), gate (2), source (3).