Integrated Device Technology 700MHz,FemtoClock VCXO Based SONET/SDH Jitter Attenuator 843002AKI-41LF

Description
The 843002I-41 is a PLL based synchronous clock generator that is optimized for SONET / SDH line card applications where jitter attenuation and frequency translation is needed. The device contains two internal PLL stages that are cascaded in series. The first PLL stage uses a VCXO which is optimized to provide reference clock jitter attenuation and to be jitter tolerant, and to provide a stable reference clock for the 2nd PLL stage (typically 19.44MHz). The second PLL stage provides additional frequency multiplication (x32), and it maintains low output jitter by using a low phase noise FemtoClock® VCO . PLL multiplication ratios are selected from internal lookup tables using device input selection pins. The device performance and the PLL multiplication ratios are optimized to support non- FEC (non-Forward Error Correction) SONET / SDH applications with rates up to OC -48 ( SONET ) or STM -16 ( SDH ). The VCXO requires the use of an external, inexpensive pullable crystal. VCXO PLL uses external passive loop filter components which are used to optimize the PLL loop bandwidth and damping characteristics for the given line card application. The 843002I-41 includes two clock input ports. Each one can accept either a single-ended or differential input. Each input port also includes an activity detector circuit, which reports input clock activity through the LOR0 and LOR1 logic output pins. The two input ports feed an input selection mux. "Hitless switching" is accomplished through proper filter tuning. Jitter transfer and wander characteristics are influenced by loop filter tuning, and phase transient performance is influenced by both loop filter tuning and alignment error between the two reference clocks. Typical 843002I-41 configuration in SONET / SDH Systems: VCXO 19.44MHz crystal Input Reference clock frequency selections: 19.44MHz, 38.88MHz, 77.76MHz, 155.52MHz, 311.04MHz, 622.08MHz Output clock frequency selections: 19.44MHz, 77.76MHz, 155.52MHz, 311.04MHz, 622.08MHz, Hi-Z
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Description
The 843002I-41 is a PLL based synchronous clock generator that is optimized for SONET / SDH line card applications where jitter attenuation and frequency translation is needed. The device contains two internal PLL stages that are cascaded in series. The first PLL stage uses a VCXO which is optimized to provide reference clock jitter attenuation and to be jitter tolerant, and to provide a stable reference clock for the 2nd PLL stage (typically 19.44MHz). The second PLL stage provides additional frequency multiplication (x32), and it maintains low output jitter by using a low phase noise FemtoClock® VCO . PLL multiplication ratios are selected from internal lookup tables using device input selection pins. The device performance and the PLL multiplication ratios are optimized to support non- FEC (non-Forward Error Correction) SONET / SDH applications with rates up to OC -48 ( SONET ) or STM -16 ( SDH ). The VCXO requires the use of an external, inexpensive pullable crystal. VCXO PLL uses external passive loop filter components which are used to optimize the PLL loop bandwidth and damping characteristics for the given line card application. The 843002I-41 includes two clock input ports. Each one can accept either a single-ended or differential input. Each input port also includes an activity detector circuit, which reports input clock activity through the LOR0 and LOR1 logic output pins. The two input ports feed an input selection mux. "Hitless switching" is accomplished through proper filter tuning. Jitter transfer and wander characteristics are influenced by loop filter tuning, and phase transient performance is influenced by both loop filter tuning and alignment error between the two reference clocks. Typical 843002I-41 configuration in SONET / SDH Systems: VCXO 19.44MHz crystal Input Reference clock frequency selections: 19.44MHz, 38.88MHz, 77.76MHz, 155.52MHz, 311.04MHz, 622.08MHz Output clock frequency selections: 19.44MHz, 77.76MHz, 155.52MHz, 311.04MHz, 622.08MHz, Hi-Z
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Suppliers

Company
Product
Description
Supplier Links
700MHz,FemtoClock VCXO Based SONET/SDH Jitter Attenuator - 843002AKI-41LF - Integrated Device Technology
San Jose, CA, USA
700MHz,FemtoClock VCXO Based SONET/SDH Jitter Attenuator
843002AKI-41LF
700MHz,FemtoClock VCXO Based SONET/SDH Jitter Attenuator 843002AKI-41LF
The 843002I-41 is a PLL based synchronous clock generator that is optimized for SONET / SDH line card applications where jitter attenuation and frequency translation is needed. The device contains two internal PLL stages that are cascaded in series. The first PLL stage uses a VCXO which is optimized to provide reference clock jitter attenuation and to be jitter tolerant, and to provide a stable reference clock for the 2nd PLL stage (typically 19.44MHz). The second PLL stage provides additional frequency multiplication (x32), and it maintains low output jitter by using a low phase noise FemtoClock® VCO . PLL multiplication ratios are selected from internal lookup tables using device input selection pins. The device performance and the PLL multiplication ratios are optimized to support non- FEC (non-Forward Error Correction) SONET / SDH applications with rates up to OC -48 ( SONET ) or STM -16 ( SDH ). The VCXO requires the use of an external, inexpensive pullable crystal. VCXO PLL uses external passive loop filter components which are used to optimize the PLL loop bandwidth and damping characteristics for the given line card application. The 843002I-41 includes two clock input ports. Each one can accept either a single-ended or differential input. Each input port also includes an activity detector circuit, which reports input clock activity through the LOR0 and LOR1 logic output pins. The two input ports feed an input selection mux. "Hitless switching" is accomplished through proper filter tuning. Jitter transfer and wander characteristics are influenced by loop filter tuning, and phase transient performance is influenced by both loop filter tuning and alignment error between the two reference clocks. Typical 843002I-41 configuration in SONET / SDH Systems: VCXO 19.44MHz crystal Input Reference clock frequency selections: 19.44MHz, 38.88MHz, 77.76MHz, 155.52MHz, 311.04MHz, 622.08MHz Output clock frequency selections: 19.44MHz, 77.76MHz, 155.52MHz, 311.04MHz, 622.08MHz, Hi-Z

The 843002I-41 is a PLL based synchronous clock generator that is optimized for SONET / SDH line card applications where jitter attenuation and frequency translation is needed. The device contains two internal PLL stages that are cascaded in series. The first PLL stage uses a VCXO which is optimized to provide reference clock jitter attenuation and to be jitter tolerant, and to provide a stable reference clock for the 2nd PLL stage (typically 19.44MHz). The second PLL stage provides additional frequency multiplication (x32), and it maintains low output jitter by using a low phase noise FemtoClock® VCO . PLL multiplication ratios are selected from internal lookup tables using device input selection pins. The device performance and the PLL multiplication ratios are optimized to support non- FEC (non-Forward Error Correction) SONET / SDH applications with rates up to OC -48 ( SONET ) or STM -16 ( SDH ). The VCXO requires the use of an external, inexpensive pullable crystal. VCXO PLL uses external passive loop filter components which are used to optimize the PLL loop bandwidth and damping characteristics for the given line card application.
The 843002I-41 includes two clock input ports. Each one can accept either a single-ended or differential input. Each input port also includes an activity detector circuit, which reports input clock activity through the LOR0 and LOR1 logic output pins. The two input ports feed an input selection mux. "Hitless switching" is accomplished through proper filter tuning. Jitter transfer and wander characteristics are influenced by loop filter tuning, and phase transient performance is influenced by both loop filter tuning and alignment error between the two reference clocks.
Typical 843002I-41 configuration in SONET / SDH Systems:

  • VCXO 19.44MHz crystal
  • Input Reference clock frequency selections:
    19.44MHz, 38.88MHz, 77.76MHz, 155.52MHz, 311.04MHz, 622.08MHz
  • Output clock frequency selections:
    19.44MHz, 77.76MHz, 155.52MHz, 311.04MHz, 622.08MHz, Hi-Z
Supplier's Site Datasheet
Clock/Timing - Clock/Timing - Clock Generators, PLLs, Frequency Synthesizers - 843002AKI-41LF - 1133970-843002AKI-41LF - Win Source Electronics
Laguna Hills, CA, United States
Clock/Timing - Clock/Timing - Clock Generators, PLLs, Frequency Synthesizers - 843002AKI-41LF
1133970-843002AKI-41LF
Clock/Timing - Clock/Timing - Clock Generators, PLLs, Frequency Synthesizers - 843002AKI-41LF 1133970-843002AKI-41LF
Manufacturer: IDT, Integrated Device Technology Inc Win Source Part Number: 1133970-843002AKI-41 LF Packaging: Tray Type: Clock Generator, Clock Synchronizer, Frequency Translator, Jitter Attenuator, Multiplexer Mounting Style: SMD Frequency - Max: 700MHz Input: HCSL, LVCMOS, LVDS, LVHSTL, LVPECL, LVTTL, SSTL Output: LVPECL PLL: Yes with Bypass Divider/Multiplier: Yes/Yes Part Status: Last Time Buy Categories: Integrated Circuits Supplier Device Package: 32-VFQFPN (5x5) Temperature Range - Operating: -40°C ~ 85°C Manufacturer Homepage: www.idt.com Manufacturer Package: 32-VFQFN Exposed Pad Popularity: Medium Fake Threat In the Open Market: 43 pct. Supply and Demand Status: Limited Family Part Number: ICS843002-41 Manufacturer Pack Quantity: 490 MSL Level: 3 (168 Hours) Supply Voltage (V): 3.135V ~ 3.465V

Manufacturer: IDT, Integrated Device Technology Inc
Win Source Part Number: 1133970-843002AKI-41LF
Packaging: Tray
Type: Clock Generator, Clock Synchronizer, Frequency Translator, Jitter Attenuator, Multiplexer
Mounting Style: SMD
Frequency - Max: 700MHz
Input: HCSL, LVCMOS, LVDS, LVHSTL, LVPECL, LVTTL, SSTL
Output: LVPECL
PLL: Yes with Bypass
Divider/Multiplier: Yes/Yes
Part Status: Last Time Buy
Categories: Integrated Circuits
Supplier Device Package: 32-VFQFPN (5x5)
Temperature Range - Operating: -40°C ~ 85°C
Manufacturer Homepage: www.idt.com
Manufacturer Package: 32-VFQFN Exposed Pad
Popularity: Medium
Fake Threat In the Open Market: 43 pct.
Supply and Demand Status: Limited
Family Part Number: ICS843002-41
Manufacturer Pack Quantity: 490
MSL Level: 3 (168 Hours)
Supply Voltage (V): 3.135V ~ 3.465V

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Technical Specifications

  Integrated Device Technology Win Source Electronics
Product Category IC Phase-locked Loops (PLL) IC Clocks
Product Number 843002AKI-41LF 1133970-843002AKI-41LF
Product Name 700MHz,FemtoClock VCXO Based SONET/SDH Jitter Attenuator Clock/Timing - Clock/Timing - Clock Generators, PLLs, Frequency Synthesizers - 843002AKI-41LF
Bus Interface LVPECL; LVPECL ECL; PECL; LVPECL; LVPECL
Package Type Surface Mount; VFQFPN Surface Mount
Supply Voltage 3.3 volts 3.13 to 3.46 volts
Frequency 19.44 to 622 MHz 700 MHz
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