Integrated Device Technology Synchronous Ethernet WAN PLL 82V3358EDG

Description
The 82V3358 is an integrated, single-chip solution for the Synchronous Equipment Timing Source for Stratum 3, SMC , 4E and 4 clocks in SONET / SDH equipments, DWDM and Wireless base station, such as GSM , 3G, DSL concentrator, Router and Access Network applications.The device supports three types of input clock sources: recovered clock from STM -N or OC -n, PDH network synchronization timing and external synchronization reference timing. Based on ITU -T G.783 and Telcordia GR -253- CORE , the device consists of T0 and T4 paths. The T0 path is a high quality and highly configurable path to provide system clock for node timing synchronization within a SONET / SDH network. The T4 path is simpler and less configurable for equipment synchronization. The T4 path locks independently from the T0 path or locks to the T0 path. An input clock is automatically or manually selected for T0 and T4 each for DPLL locking. Both the T0 and T4 paths support three primary operating modes: Free-Run, Locked and Holdover. In Free-Run mode, the DPLL refers to the master clock. In Locked mode, the DPLL locks to the selected input clock. In Holdover mode, the DPLL resorts to the frequency data acquired in Locked mode. Whatever the operating mode is, the DPLL gives a stable performance without being affected by operating conditions or silicon process variations. If the DPLL outputs are processed by T0/T4 APLL , the outputs of the device will be in a better jitter/wander performance. The device provides programmable DPLL bandwidths: 0.1 Hz to 560 Hz in 11 steps and damping factors: 1.2 to 20 in 5 steps. Different settings cover all SONET / SDH clock synchronization requirements. A high stable input is required for the master clock in different applications. The master clock is used as a reference clock for all the internal circuits in the device. It can be calibrated within ±741 ppm. All the read/write registers are accessed through a serial microprocessor interface. The device supports Serial microprocessor interface mode only.
  • Synchronous Ethernet WAN PLL - 82V3358EDG - Integrated Device Technology
    Integrated Device Technology
  • Clock and Timing IC - 763-82V3358EDG - ERSAELECTRONICS PTE. LTD.
    ERSAELECTRONICS PTE. LTD.
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Description
The 82V3358 is an integrated, single-chip solution for the Synchronous Equipment Timing Source for Stratum 3, SMC , 4E and 4 clocks in SONET / SDH equipments, DWDM and Wireless base station, such as GSM , 3G, DSL concentrator, Router and Access Network applications.The device supports three types of input clock sources: recovered clock from STM -N or OC -n, PDH network synchronization timing and external synchronization reference timing. Based on ITU -T G.783 and Telcordia GR -253- CORE , the device consists of T0 and T4 paths. The T0 path is a high quality and highly configurable path to provide system clock for node timing synchronization within a SONET / SDH network. The T4 path is simpler and less configurable for equipment synchronization. The T4 path locks independently from the T0 path or locks to the T0 path. An input clock is automatically or manually selected for T0 and T4 each for DPLL locking. Both the T0 and T4 paths support three primary operating modes: Free-Run, Locked and Holdover. In Free-Run mode, the DPLL refers to the master clock. In Locked mode, the DPLL locks to the selected input clock. In Holdover mode, the DPLL resorts to the frequency data acquired in Locked mode. Whatever the operating mode is, the DPLL gives a stable performance without being affected by operating conditions or silicon process variations. If the DPLL outputs are processed by T0/T4 APLL , the outputs of the device will be in a better jitter/wander performance. The device provides programmable DPLL bandwidths: 0.1 Hz to 560 Hz in 11 steps and damping factors: 1.2 to 20 in 5 steps. Different settings cover all SONET / SDH clock synchronization requirements. A high stable input is required for the master clock in different applications. The master clock is used as a reference clock for all the internal circuits in the device. It can be calibrated within ±741 ppm. All the read/write registers are accessed through a serial microprocessor interface. The device supports Serial microprocessor interface mode only.
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Suppliers

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Product
Description
Supplier Links
Synchronous Ethernet WAN PLL - 82V3358EDG - Integrated Device Technology
Integrated Device Technology
San Jose, CA, USA
Synchronous Ethernet WAN PLL
82V3358EDG
Synchronous Ethernet WAN PLL 82V3358EDG
The 82V3358 is an integrated, single-chip solution for the Synchronous Equipment Timing Source for Stratum 3, SMC , 4E and 4 clocks in SONET / SDH equipments, DWDM and Wireless base station, such as GSM , 3G, DSL concentrator, Router and Access Network applications.The device supports three types of input clock sources: recovered clock from STM -N or OC -n, PDH network synchronization timing and external synchronization reference timing. Based on ITU -T G.783 and Telcordia GR -253- CORE , the device consists of T0 and T4 paths. The T0 path is a high quality and highly configurable path to provide system clock for node timing synchronization within a SONET / SDH network. The T4 path is simpler and less configurable for equipment synchronization. The T4 path locks independently from the T0 path or locks to the T0 path. An input clock is automatically or manually selected for T0 and T4 each for DPLL locking. Both the T0 and T4 paths support three primary operating modes: Free-Run, Locked and Holdover. In Free-Run mode, the DPLL refers to the master clock. In Locked mode, the DPLL locks to the selected input clock. In Holdover mode, the DPLL resorts to the frequency data acquired in Locked mode. Whatever the operating mode is, the DPLL gives a stable performance without being affected by operating conditions or silicon process variations. If the DPLL outputs are processed by T0/T4 APLL , the outputs of the device will be in a better jitter/wander performance. The device provides programmable DPLL bandwidths: 0.1 Hz to 560 Hz in 11 steps and damping factors: 1.2 to 20 in 5 steps. Different settings cover all SONET / SDH clock synchronization requirements. A high stable input is required for the master clock in different applications. The master clock is used as a reference clock for all the internal circuits in the device. It can be calibrated within ±741 ppm. All the read/write registers are accessed through a serial microprocessor interface. The device supports Serial microprocessor interface mode only.

The 82V3358 is an integrated, single-chip solution for the Synchronous Equipment Timing Source for Stratum 3, SMC , 4E and 4 clocks in SONET / SDH equipments, DWDM and Wireless base station, such as GSM , 3G, DSL concentrator, Router and Access Network applications.The device supports three types of input clock sources: recovered clock from STM -N or OC -n, PDH network synchronization timing and external synchronization reference timing. Based on ITU -T G.783 and Telcordia GR -253- CORE , the device consists of T0 and T4 paths. The T0 path is a high quality and highly configurable path to provide system clock for node timing synchronization within a SONET / SDH network. The T4 path is simpler and less configurable for equipment synchronization. The T4 path locks independently from the T0 path or locks to the T0 path. An input clock is automatically or manually selected for T0 and T4 each for DPLL locking. Both the T0 and T4 paths support three primary operating modes: Free-Run, Locked and Holdover. In Free-Run mode, the DPLL refers to the master clock. In Locked mode, the DPLL locks to the selected input clock. In Holdover mode, the DPLL resorts to the frequency data acquired in Locked mode. Whatever the operating mode is, the DPLL gives a stable performance without being affected by operating conditions or silicon process variations. If the DPLL outputs are processed by T0/T4 APLL , the outputs of the device will be in a better jitter/wander performance. The device provides programmable DPLL bandwidths: 0.1 Hz to 560 Hz in 11 steps and damping factors: 1.2 to 20 in 5 steps. Different settings
cover all SONET / SDH clock synchronization requirements. A high stable input is required for the master clock in different applications. The master clock is used as a reference clock for all the internal circuits in the device. It can be calibrated within ±741 ppm. All the read/write registers are accessed through a serial microprocessor interface. The device supports Serial microprocessor interface mode only.

Supplier's Site Datasheet
Clock and Timing IC - 763-82V3358EDG - ERSAELECTRONICS PTE. LTD.
ERSAELECTRONICS PTE. LTD.
Singapore
Clock and Timing IC
763-82V3358EDG
Clock and Timing IC 763-82V3358EDG
SYNCHRONOUS ETHERNET WAN PLL | IC PLL WAN SYNC ETHERNET 64TQFP Product overview: 82V3358EDG from Integrated Device Technology (IDT) is a Clock and Timing IC for clock generation, timing distribution, synchronization, RF systems, communication hardware, and digital boards. It is useful for engineers and buyers comparing datasheets, replacement parts, BOM lines, package options, lifecycle status, and procurement availability. Key searchable attributes include key electrical ratings, package details, and application requirements. Search-friendly keywords include clock generator, oscillator, timing, synchronization, Clock and Timing IC, Application Specific Clock/Timing ICs. This listing supports clearer product discovery for industrial, commercial, repair, automation, power, sensing, and embedded system projects. Product number 763-82V3358EDG can be used for catalog matching and distributor lookup.

SYNCHRONOUS ETHERNET WAN PLL | IC PLL WAN SYNC ETHERNET 64TQFP Product overview: 82V3358EDG from Integrated Device Technology (IDT) is a Clock and Timing IC for clock generation, timing distribution, synchronization, RF systems, communication hardware, and digital boards. It is useful for engineers and buyers comparing datasheets, replacement parts, BOM lines, package options, lifecycle status, and procurement availability. Key searchable attributes include key electrical ratings, package details, and application requirements. Search-friendly keywords include clock generator, oscillator, timing, synchronization, Clock and Timing IC, Application Specific Clock/Timing ICs. This listing supports clearer product discovery for industrial, commercial, repair, automation, power, sensing, and embedded system projects. Product number 763-82V3358EDG can be used for catalog matching and distributor lookup.

Supplier's Site

Technical Specifications

  Integrated Device Technology ERSAELECTRONICS PTE. LTD.
Product Category IC Phase-locked Loops (PLL) IC Timers
Product Number 82V3358EDG 763-82V3358EDG
Product Name Synchronous Ethernet WAN PLL Clock and Timing IC
Bus Interface LVPECL; LVDS; LVPECL,LVDS,LVCMOS CMOS, LVDS, PECL
Package Type Surface Mount; TQFP Tray
Supply Voltage 3.3 volts
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