Integrated Device Technology 32K x 9 SuperSync FIFO, 5.0V 72271LA10PFG8

Description
The 72271 is a 32K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin ( FS ) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK , is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSync family.)
Datasheet
Description
The 72271 is a 32K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin ( FS ) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK , is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSync family.)
Datasheet

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32K x 9 SuperSync FIFO, 5.0V - 72271LA10PFG8 - Integrated Device Technology
San Jose, CA, USA
32K x 9 SuperSync FIFO, 5.0V
72271LA10PFG8
32K x 9 SuperSync FIFO, 5.0V 72271LA10PFG8
The 72271 is a 32K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin ( FS ) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK , is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSync family.)

The 72271 is a 32K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin ( FS ) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK , is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSync family.)

Supplier's Site Datasheet

Technical Specifications

  Integrated Device Technology
Product Category Memory Chips
Product Number 72271LA10PFG8
Product Name 32K x 9 SuperSync FIFO, 5.0V
Memory Category FIFO
Logic Family TTL
Data Rate 100 MHz
Operating Temperature 0 to 70 C (32 to 158 F)
Density 288 kbits
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