The application transmits a BERT pattern using the simplest ATM Adaptation Layer, i.e. AAL0. The BERT pattern is inserted in its entirety into the 48 byte payload of the cell. This is shown graphically below. Cells are either “BERT payload” or “idle” cells. Note that “cell headers” and payload can overlap the framing position.
In contrast to traditional BERT, ATM BERT is done at the ATM layer and can be performed all of the way across the virtual circuit to the far-end customer-premise site. Often, user traffic may be routed through several CO sites before reaching the first ATM edge switch. Each of these additional routes adds to the potential for errors. Traditional BERTs may only verify the local loop to the first CO and neglect to verify the connections between the intermediate COs. Thus ATM BERT allows for end-to-end verification of the circuit’s reliability.
The application allows traffic generation and verification, bit error insertion, looping back incoming traffic, and configuring ATM header fields such as virtual path and circuit identifier values, GFC, PT, and CLP for UNI & NNI interfaces.
The application is capable of testing Pseudo Random Bit Sequence (PRBS) patterns, fixed patterns like all ones, all zeroes, alternate ones & zeroes, 1:1, 1:7, and user-defined bit patterns. In addition, single bit error insertion rate, error insertion from 10-2 to 10-9, invert, and scrambling options are provided for payload.
Main Features
Capable of generating/receiving ATM traffic
Support user-defined ATM header configuration for GFC, VPI, VCI, PT, CLP
User-defined traffic rate to the accuracy of 1% of total bandwidth.
Supports different QRSS, PRBS patterns 29-1, 211-1, 215-1, 220-1, 223-1, All one’s, All zero’s, alternate 1’s and 0’s, 1:1, 1:7, & User-defined patterns. User defined patterns length can be 3 to 32 bits in length.
Supports inverting, and scrambling payload data. Scrambling is according to ITU-T G.804
Supports single bit error insertion, and error rate insertion.
Provides ATM QoS measurement (Bit error count/ Rate/Seconds, Sync Loss, No Rx data,… )
Provides ATM Statistics (total cell count, rejected / pass / idle cell counts, cell rate, and HEC error count).
Error and Alarm LEDs for easy analysis.
Supports testing on multiple cards simultaneously with consolidated result view.
Tx and Rx settings for multiple cards can be independently controlled or coupled.
Capability to save and load the configuration settings.
The application transmits a BERT pattern using the simplest ATM Adaptation Layer, i.e. AAL0. The BERT pattern is inserted in its entirety into the 48 byte payload of the cell. This is shown graphically below. Cells are either “BERT payload” or “idle” cells. Note that “cell headers” and payload can overlap the framing position.
In contrast to traditional BERT, ATM BERT is done at the ATM layer and can be performed all of the way across the virtual circuit to the far-end customer-premise site. Often, user traffic may be routed through several CO sites before reaching the first ATM edge switch. Each of these additional routes adds to the potential for errors. Traditional BERTs may only verify the local loop to the first CO and neglect to verify the connections between the intermediate COs. Thus ATM BERT allows for end-to-end verification of the circuit’s reliability.
The application allows traffic generation and verification, bit error insertion, looping back incoming traffic, and configuring ATM header fields such as virtual path and circuit identifier values, GFC, PT, and CLP for UNI & NNI interfaces.
The application is capable of testing Pseudo Random Bit Sequence (PRBS) patterns, fixed patterns like all ones, all zeroes, alternate ones & zeroes, 1:1, 1:7, and user-defined bit patterns. In addition, single bit error insertion rate, error insertion from 10-2 to 10-9, invert, and scrambling options are provided for payload.
Main Features
- Capable of generating/receiving ATM traffic
- Support user-defined ATM header configuration for GFC, VPI, VCI, PT, CLP
- User-defined traffic rate to the accuracy of 1% of total bandwidth.
- Supports different QRSS, PRBS patterns 29-1, 211-1, 215-1, 220-1, 223-1, All one’s, All zero’s, alternate 1’s and 0’s, 1:1, 1:7, & User-defined patterns. User defined patterns length can be 3 to 32 bits in length.
- Supports inverting, and scrambling payload data. Scrambling is according to ITU-T G.804
- Supports single bit error insertion, and error rate insertion.
- Provides ATM QoS measurement (Bit error count/ Rate/Seconds, Sync Loss, No Rx data,… )
- Provides ATM Statistics (total cell count, rejected / pass / idle cell counts, cell rate, and HEC error count).
- Error and Alarm LEDs for easy analysis.
- Supports testing on multiple cards simultaneously with consolidated result view.
- Tx and Rx settings for multiple cards can be independently controlled or coupled.
- Capability to save and load the configuration settings.
