Allied Electronics, Inc. TRANSCEIVER; TTL; 20-LEAD PDIP; 7 V; 48MA (TYP.); 2 V; 0.8 V; 2 V (MIN.) 70146963

Description
TRANSCEIVER; TTL; 20-LEAD PDIP; 7 V; 48 MA (TYP.); 2 V; 0.8 V; 2 V (MIN.) These octal bus transceivers are designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements. The devices allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can disable the device so that the buses are effectively isolated. 3-State Outputs Drive Bus Lines Directly PNP Inputs Reduce dc Loading on Bus Lines. Hysteresis at Bus Inputs Improves Noise Margins. Typical Propagation Delay Times Port to Port, 8 ns.
Description
TRANSCEIVER; TTL; 20-LEAD PDIP; 7 V; 48 MA (TYP.); 2 V; 0.8 V; 2 V (MIN.) These octal bus transceivers are designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements. The devices allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can disable the device so that the buses are effectively isolated. 3-State Outputs Drive Bus Lines Directly PNP Inputs Reduce dc Loading on Bus Lines. Hysteresis at Bus Inputs Improves Noise Margins. Typical Propagation Delay Times Port to Port, 8 ns.

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TRANSCEIVER; TTL; 20-LEAD PDIP; 7 V; 48MA (TYP.); 2 V; 0.8 V; 2 V (MIN.) - 70146963 - Allied Electronics, Inc.
Fort Worth, TX, USA
TRANSCEIVER; TTL; 20-LEAD PDIP; 7 V; 48MA (TYP.); 2 V; 0.8 V; 2 V (MIN.)
70146963
TRANSCEIVER; TTL; 20-LEAD PDIP; 7 V; 48MA (TYP.); 2 V; 0.8 V; 2 V (MIN.) 70146963
TRANSCEIVER; TTL; 20-LEAD PDIP; 7 V; 48 MA (TYP.); 2 V; 0.8 V; 2 V (MIN.) These octal bus transceivers are designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements. The devices allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can disable the device so that the buses are effectively isolated. 3-State Outputs Drive Bus Lines Directly PNP Inputs Reduce dc Loading on Bus Lines. Hysteresis at Bus Inputs Improves Noise Margins. Typical Propagation Delay Times Port to Port, 8 ns.

TRANSCEIVER; TTL; 20-LEAD PDIP; 7 V; 48 MA (TYP.); 2 V; 0.8 V; 2 V (MIN.)
These octal bus transceivers are designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements. The devices allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can disable the device so that the buses are effectively isolated.

  • 3-State Outputs Drive Bus Lines Directly
  • PNP Inputs Reduce dc Loading on Bus Lines.
  • Hysteresis at Bus Inputs Improves Noise Margins.
  • Typical Propagation Delay Times Port to Port, 8 ns.
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Technical Specifications

  Allied Electronics, Inc.
Product Category IC Interfaces
Product Number 70146963
Product Name TRANSCEIVER; TTL; 20-LEAD PDIP; 7 V; 48MA (TYP.); 2 V; 0.8 V; 2 V (MIN.)
Device Type Transceiver; Logic
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