Data Delay Devices, Inc. Fixed 5-Tap TTL/CMOS Monolithic Delay Line 3D7105

Description
FEATURES • All-silicon, low-power CMOS technology • TTL/CMOS compatible inputs and outputs • Vapor phase, IR and wave solderable • Auto-insertable (DIP pkg.) • Low ground bounce noise • Leading- and trailing-edge accuracy • Delay range: .75 through 80ns • Delay tolerance: 5% or 1ns • Temperature stability: ±3% typical (0C-70C) • Vdd stability: ±1% typical (4.75V-5.25V) • Minimum input pulse width: 30% of total delay • 14-pin DIP and 16-pin SOIC available as drop-in replacements for hybrid delay lines
Datasheet
Description
FEATURES • All-silicon, low-power CMOS technology • TTL/CMOS compatible inputs and outputs • Vapor phase, IR and wave solderable • Auto-insertable (DIP pkg.) • Low ground bounce noise • Leading- and trailing-edge accuracy • Delay range: .75 through 80ns • Delay tolerance: 5% or 1ns • Temperature stability: ±3% typical (0C-70C) • Vdd stability: ±1% typical (4.75V-5.25V) • Minimum input pulse width: 30% of total delay • 14-pin DIP and 16-pin SOIC available as drop-in replacements for hybrid delay lines
Datasheet

Suppliers

Company
Product
Description
Supplier Links
Fixed 5-Tap TTL/CMOS Monolithic Delay Line - 3D7105 - Data Delay Devices, Inc.
Clifton, NJ, USA
Fixed 5-Tap TTL/CMOS Monolithic Delay Line
3D7105
Fixed 5-Tap TTL/CMOS Monolithic Delay Line 3D7105
FEATURES • All-silicon, low-power CMOS technology • TTL/CMOS compatible inputs and outputs • Vapor phase, IR and wave solderable • Auto-insertable (DIP pkg.) • Low ground bounce noise • Leading- and trailing-edge accuracy • Delay range: .75 through 80ns • Delay tolerance: 5% or 1ns • Temperature stability: ±3% typical (0C-70C) • Vdd stability: ±1% typical (4.75V-5.25V) • Minimum input pulse width: 30% of total delay • 14-pin DIP and 16-pin SOIC available as drop-in replacements for hybrid delay lines

FEATURES
• All-silicon, low-power CMOS
technology
• TTL/CMOS compatible
inputs and outputs
• Vapor phase, IR and wave
solderable
• Auto-insertable (DIP pkg.)
• Low ground bounce noise
• Leading- and trailing-edge accuracy
• Delay range: .75 through 80ns
• Delay tolerance: 5% or 1ns
• Temperature stability: ±3% typical (0C-70C)
• Vdd stability: ±1% typical (4.75V-5.25V)
• Minimum input pulse width: 30% of total delay
• 14-pin DIP and 16-pin SOIC available as drop-in
replacements for hybrid delay lines

Datasheet

Technical Specifications

  Data Delay Devices, Inc.
Product Category Delay Lines
Product Number 3D7105
Product Name Fixed 5-Tap TTL/CMOS Monolithic Delay Line
Delay Line Technology Digital
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