This EEPROM memory macro is a nonvolatile register that can be configured for 8 to 64 bits. It is implemented with CSS’s Classic NV Latch cell that features a single cycle store function. Read mode current is < 1uA. Numerous serial and parallel interface options for entering data and reading out the contents of the NV register are available. This memory macro cell is designed for AMI’s 0.5 micron, CMOS process. For more information, please refer to the following documents or contact CSS.
| Custom Silicon Solutions, Inc. | |
|---|---|
| Product Category | Memory Chips |
| Product Number | NV Register |
| Product Name | IP Products |
| Memory Category | EEPROM |
