Cirrus Logic, Inc. Stereo ADC WM8781

Description
The WM8781 is a high performance, low cost stereo audio ADC designed for recordable media applications. The device offers stereo line level inputs along with two control input pins (FORMAT, IWL) to allow operation of the audio interface in three industry standard modes. An internal op-amp is integrated on the front end of the chip to accommodate analog input signals greater than 1Vrms. The device also has a high pass filter to remove residual DC offsets. WM8781 offers Master or Slave mode clocking schemes. A control input pin M/S is used to allow Slave mode operation or Master mode operation. A stereo 24-bit multi-bit delta-sigma ADC is used with 128x, 64x or 32x over-sampling, according to sample rate. Digital audio output word lengths from 16-24 bits and sampling rates from 8 kHz to 192 kHz are supported. The device is a hardware controlled device and is supplied in a 20-lead SSOP package. Features SNR 102 dB (‘A’ weighted @ 48 kHz) THD -90 dB (at –1 dB) sampling frequency: 8 – 192 kHz master or slave clocking mode system clock (MCLK): 128fs, 192fs, 256fs, 384fs, 512fs, 768fs audio data interface modes 16-24 bit I²S, 16-24 bit left, 16-24 bit right justified supply voltages analog 2.7 to 5.5V digital core: 2.7V to 3.6V 20-lead SSOP package
Datasheet
Description
The WM8781 is a high performance, low cost stereo audio ADC designed for recordable media applications. The device offers stereo line level inputs along with two control input pins (FORMAT, IWL) to allow operation of the audio interface in three industry standard modes. An internal op-amp is integrated on the front end of the chip to accommodate analog input signals greater than 1Vrms. The device also has a high pass filter to remove residual DC offsets. WM8781 offers Master or Slave mode clocking schemes. A control input pin M/S is used to allow Slave mode operation or Master mode operation. A stereo 24-bit multi-bit delta-sigma ADC is used with 128x, 64x or 32x over-sampling, according to sample rate. Digital audio output word lengths from 16-24 bits and sampling rates from 8 kHz to 192 kHz are supported. The device is a hardware controlled device and is supplied in a 20-lead SSOP package. Features SNR 102 dB (‘A’ weighted @ 48 kHz) THD -90 dB (at –1 dB) sampling frequency: 8 – 192 kHz master or slave clocking mode system clock (MCLK): 128fs, 192fs, 256fs, 384fs, 512fs, 768fs audio data interface modes 16-24 bit I²S, 16-24 bit left, 16-24 bit right justified supply voltages analog 2.7 to 5.5V digital core: 2.7V to 3.6V 20-lead SSOP package
Datasheet

Suppliers

Company
Product
Description
Supplier Links
Stereo ADC - WM8781 - Cirrus Logic, Inc.
Austin, TX, USA
Stereo ADC
WM8781
Stereo ADC WM8781
The WM8781 is a high performance, low cost stereo audio ADC designed for recordable media applications. The device offers stereo line level inputs along with two control input pins (FORMAT, IWL) to allow operation of the audio interface in three industry standard modes. An internal op-amp is integrated on the front end of the chip to accommodate analog input signals greater than 1Vrms. The device also has a high pass filter to remove residual DC offsets. WM8781 offers Master or Slave mode clocking schemes. A control input pin M/S is used to allow Slave mode operation or Master mode operation. A stereo 24-bit multi-bit delta-sigma ADC is used with 128x, 64x or 32x over-sampling, according to sample rate. Digital audio output word lengths from 16-24 bits and sampling rates from 8 kHz to 192 kHz are supported. The device is a hardware controlled device and is supplied in a 20-lead SSOP package. Features SNR 102 dB (‘A’ weighted @ 48 kHz) THD -90 dB (at –1 dB) sampling frequency: 8 – 192 kHz master or slave clocking mode system clock (MCLK): 128fs, 192fs, 256fs, 384fs, 512fs, 768fs audio data interface modes 16-24 bit I²S, 16-24 bit left, 16-24 bit right justified supply voltages analog 2.7 to 5.5V digital core: 2.7V to 3.6V 20-lead SSOP package

The WM8781 is a high performance, low cost stereo audio ADC designed for recordable media applications. The device offers stereo line level inputs along with two control input pins (FORMAT, IWL) to allow operation of the audio interface in three industry standard modes. An internal op-amp is integrated on the front end of the chip to accommodate analog input signals greater than 1Vrms. The device also has a high pass filter to remove residual DC offsets. WM8781 offers Master or Slave mode clocking schemes. A control input pin M/S is used to allow Slave mode operation or Master mode operation. A stereo 24-bit multi-bit delta-sigma ADC is used with 128x, 64x or 32x over-sampling, according to sample rate. Digital audio output word lengths from 16-24 bits and sampling rates from 8 kHz to 192 kHz are supported. The device is a hardware controlled device and is supplied in a 20-lead SSOP package.

Features

  • SNR 102 dB (‘A’ weighted @ 48 kHz)
  • THD -90 dB (at –1 dB)
  • sampling frequency: 8 – 192 kHz
  • master or slave clocking mode
  • system clock (MCLK): 128fs, 192fs, 256fs, 384fs, 512fs, 768fs
  • audio data interface modes
    • 16-24 bit I²S, 16-24 bit left, 16-24 bit right justified
  • supply voltages
    • analog 2.7 to 5.5V
    • digital core: 2.7V to 3.6V
  • 20-lead SSOP package
Supplier's Site Datasheet

Technical Specifications

  Cirrus Logic, Inc.
Product Category Analog-to-Digital Converter (ADC) Chips
Product Number WM8781
Product Name Stereo ADC
Package Type SSOP
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