Nexperia B.V. Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state 74LVC373APW,118

Description
The 74LVC373A is an octal D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OEcauses the outputs to assume a high-impedance OFF-state. Operation of the OEinput does not affect the state of the latches. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. Features and benefits Overvoltage tolerant inputs to 5.5 V Wide supply voltage range from 1.2 V to 3.6 V CMOS low power consumption Direct interface with TTL levels High-impedance outputs when VCC = 0 V IOFF circuitry provides partial Power-down mode operation Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Specified from -40 °C to +85 °C and -40 °C to +125 °C
  • Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state - 74LVC373APW,118 - Nexperia B.V.
    Nexperia B.V.
  • Latches - 1727-3108-6-ND - DigiKey
    DigiKey
  • Latches - 1727-3108-1-ND - DigiKey
    DigiKey
  • Latches - 1727-3108-2-ND - DigiKey
    DigiKey
  • Latches - 74LVC373APW,118 - Quarktwin Technology Ltd.
    Quarktwin Technology Ltd.
  • Logic - Latches - 74LVC373APW,118 - Lingto Electronic Limited
    Lingto Electronic Limited
  • Latch, D Type Transp, 3-State, Tssop-20; Logic Family / Base Number Nexperia - 85X3024 - Newark, An Avnet Company
    Newark, An Avnet Company
Request a Quote Datasheet
Description
The 74LVC373A is an octal D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OEcauses the outputs to assume a high-impedance OFF-state. Operation of the OEinput does not affect the state of the latches. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. Features and benefits Overvoltage tolerant inputs to 5.5 V Wide supply voltage range from 1.2 V to 3.6 V CMOS low power consumption Direct interface with TTL levels High-impedance outputs when VCC = 0 V IOFF circuitry provides partial Power-down mode operation Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Specified from -40 °C to +85 °C and -40 °C to +125 °C
Request a Quote Datasheet

Suppliers

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Description
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Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state - 74LVC373APW,118 - Nexperia B.V.
Nexperia B.V.
Nijmegen, Netherlands
Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
74LVC373APW,118
Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state 74LVC373APW,118
The 74LVC373A is an octal D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OEcauses the outputs to assume a high-impedance OFF-state. Operation of the OEinput does not affect the state of the latches. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. Features and benefits Overvoltage tolerant inputs to 5.5 V Wide supply voltage range from 1.2 V to 3.6 V CMOS low power consumption Direct interface with TTL levels High-impedance outputs when VCC = 0 V IOFF circuitry provides partial Power-down mode operation Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Specified from -40 °C to +85 °C and -40 °C to +125 °C

The 74LVC373A is an octal D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OEcauses the outputs to assume a high-impedance OFF-state. Operation of the OEinput does not affect the state of the latches. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Features and benefits

  • Overvoltage tolerant inputs to 5.5 V
  • Wide supply voltage range from 1.2 V to 3.6 V
  • CMOS low power consumption
  • Direct interface with TTL levels
  • High-impedance outputs when VCC = 0 V
  • IOFF circuitry provides partial Power-down mode operation
  • Complies with JEDEC standard:
    • JESD8-7A (1.65 V to 1.95 V)
    • JESD8-5A (2.3 V to 2.7 V)
    • JESD8-C/JESD36 (2.7 V to 3.6 V)
  • ESD protection:
    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C
Supplier's Site Datasheet
Latches - 1727-3108-6-ND - DigiKey
DigiKey
Thief River Falls, MN, United States
Latches
1727-3108-6-ND
Latches 1727-3108-6-ND
D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-TSSOP

D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-TSSOP

Buy Now Datasheet
Latches - 1727-3108-1-ND - DigiKey
DigiKey
Thief River Falls, MN, United States
Latches
1727-3108-1-ND
Latches 1727-3108-1-ND
D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-TSSOP

D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-TSSOP

Buy Now Datasheet
Latches - 1727-3108-2-ND - DigiKey
DigiKey
Thief River Falls, MN, United States
Latches
1727-3108-2-ND
Latches 1727-3108-2-ND
D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-TSSOP

D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-TSSOP

Buy Now Datasheet
Latches - 74LVC373APW,118 - Quarktwin Technology Ltd.
Quarktwin Technology Ltd.
Shenzhen, Guangdong, China
Latches
74LVC373APW,118
Latches 74LVC373APW,118
D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-TSSOP

D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-TSSOP

Buy Now Datasheet
Logic - Latches - 74LVC373APW,118 - Lingto Electronic Limited
Lingto Electronic Limited
Shenzhen, China
Logic - Latches
74LVC373APW,118
Logic - Latches 74LVC373APW,118
IC OCTAL TRANSP LATCH 20-TSSOP

IC OCTAL TRANSP LATCH 20-TSSOP

Supplier's Site Datasheet
Latch, D Type Transp, 3-State, Tssop-20; Logic Family / Base Number Nexperia - 85X3024 - Newark, An Avnet Company
Newark, An Avnet Company
Chicago, IL, United States
Latch, D Type Transp, 3-State, Tssop-20; Logic Family / Base Number Nexperia
85X3024
Latch, D Type Transp, 3-State, Tssop-20; Logic Family / Base Number Nexperia 85X3024
LATCH, D TYPE TRANSP, 3-STATE, TSSOP-20; Logic Family / Base Number:74LVC373; Latch Type:D Type Transparent; IC Output Type:Tri State Non Inverted; Propagation Delay:-; Output Current:50mA; Logic Case Style:TSSOP; No. of Pins:20Pins;RoHS Compliant: Yes

LATCH, D TYPE TRANSP, 3-STATE, TSSOP-20; Logic Family / Base Number:74LVC373; Latch Type:D Type Transparent; IC Output Type:Tri State Non Inverted; Propagation Delay:-; Output Current:50mA; Logic Case Style:TSSOP; No. of Pins:20Pins;RoHS Compliant: Yes

Supplier's Site Datasheet

Technical Specifications

  Nexperia B.V. DigiKey Quarktwin Technology Ltd. Lingto Electronic Limited Newark, An Avnet Company
Product Category Logic Latches Logic Latches Logic Latches Logic Latches Logic Latches
Product Number 74LVC373APW,118 1727-3108-6-ND 74LVC373APW,118 74LVC373APW,118 85X3024
Product Name Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state Latches Latches Logic - Latches Latch, D Type Transp, 3-State, Tssop-20; Logic Family / Base Number Nexperia
Latch Type Transparent-D Transparent-D D; Transparent-D
Output Characteristics 3-State 3-State
Features ESD Protection
Supply Voltage +6.5 1.2V ~ 3.6V 3.6V; 1.2V ~ 3.6V
Operating Temperature 125 C (257 F) -40 to 125 C (-40 to 257 F) -40 to 125 C (-40 to 257 F)
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