Nexperia B.V. Dual D-type flip-flop with set and reset; positive-edge trigger 74LV74PW,112

Description
The 74LV74 is a dual positive edge triggered D-type flip-flop with individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the nQ output. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess VCC. Features and benefits Wide supply voltage range from 1.0 V to 5.5 V Optimized for low voltage applications from 1.0 V to 3.6 V CMOS low power dissipation Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Direct interface with TTL levels (2.7 V to 3.6 V) ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Specified from -40 °C to +85 °C and from -40 °C to +125 °C
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Product
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Dual D-type flip-flop with set and reset; positive-edge trigger - 74LV74PW,112 - Nexperia B.V.
Nijmegen, Netherlands
Dual D-type flip-flop with set and reset; positive-edge trigger
74LV74PW,112
Dual D-type flip-flop with set and reset; positive-edge trigger 74LV74PW,112
The 74LV74 is a dual positive edge triggered D-type flip-flop with individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the nQ output. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess VCC. Features and benefits Wide supply voltage range from 1.0 V to 5.5 V Optimized for low voltage applications from 1.0 V to 3.6 V CMOS low power dissipation Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Direct interface with TTL levels (2.7 V to 3.6 V) ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Specified from -40 °C to +85 °C and from -40 °C to +125 °C

The 74LV74 is a dual positive edge triggered D-type flip-flop with individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the nQ output. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess VCC.

Features and benefits

  • Wide supply voltage range from 1.0 V to 5.5 V
  • Optimized for low voltage applications from 1.0 V to 3.6 V
  • CMOS low power dissipation
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
  • Direct interface with TTL levels (2.7 V to 3.6 V)
  • ESD protection:
    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Supplier's Site Datasheet
Flip Flops - 1727-4106-ND - DigiKey
Thief River Falls, MN, United States
Flip Flops
1727-4106-ND
Flip Flops 1727-4106-ND
"Flip Flop 2 Element D-Type 1 Bit Positive Edge 14-TSSOP (0.173"", 4.40mm Width)"

"Flip Flop 2 Element D-Type 1 Bit Positive Edge 14-TSSOP (0.173"", 4.40mm Width)"

Buy Now Datasheet
 - 74LV74PW,112 - Rochester Electronics
Newburyport, MA, United States
74LV74PW - D Flip-Flop, LV/LV-A/LVX/H Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS, TSSOP14

74LV74PW - D Flip-Flop, LV/LV-A/LVX/H Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS, TSSOP14

Supplier's Site Datasheet
Flip Flops - 74LV74PW,112 - Quarktwin Technology Ltd.
Shenzhen, Guangdong, China
Flip Flops
74LV74PW,112
Flip Flops 74LV74PW,112
Flip Flop 2 Element D-Type 1 Bit Positive Edge 14-TSSOP (0.173", 4.40mm Width)

Flip Flop 2 Element D-Type 1 Bit Positive Edge 14-TSSOP (0.173", 4.40mm Width)

Buy Now Datasheet
Logic - Flip Flops - 74LV74PW,112 - Lingto Electronic Limited
Shenzhen, China
Logic - Flip Flops
74LV74PW,112
Logic - Flip Flops 74LV74PW,112
IC FF D-TYPE DUAL 1BIT 14TSSOP

IC FF D-TYPE DUAL 1BIT 14TSSOP

Supplier's Site Datasheet

Technical Specifications

  Nexperia B.V. DigiKey Rochester Electronics Quarktwin Technology Ltd. Lingto Electronic Limited
Product Category Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops
Product Number 74LV74PW,112 1727-4106-ND 74LV74PW,112 74LV74PW,112 74LV74PW,112
Product Name Dual D-type flip-flop with set and reset; positive-edge trigger Flip Flops Flip Flops Logic - Flip Flops
Flip-Flop Type D D D D
Triggering Positive-edge Triggered Positive-edge Triggered Positive-edge Triggered
Supply Voltage 1.2V; 1.5V; 1.8V; 2.5V; 3V; 3.3V; 3.6V; 5V; 1.0 - 5.5 1V ~ 5.5V 1V ~ 5.5V
Features ESD Protection
Propagation Delay 11 ns 17 ns
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