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Nexperia B.V. Dual D-type flip-flop with set and reset; positive edge-trigger 74HCT74BZZ

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Dual D-type flip-flop with set and reset; positive edge-trigger - 74HCT74BZZ - Nexperia B.V.
Nijmegen, Netherlands
Dual D-type flip-flop with set and reset; positive edge-trigger
74HCT74BZZ
Dual D-type flip-flop with set and reset; positive edge-trigger 74HCT74BZZ
The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition, is stored in the flip-flop and appears at the nQ output. Schmitt-trigger action in the clock input, makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC. Features and benefits Wide supply voltage range from 2.0 to 6.0 V CMOS low power dissipation High noise immunity Input levels: For 74HC74: CMOS level For 74HCT74: TTL level Symmetrical output impedance High noise immunity Balanced propagation delays Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Complies with JEDEC standards: JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V)

The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition, is stored in the flip-flop and appears at the nQ output. Schmitt-trigger action in the clock input, makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.

Features and benefits

  • Wide supply voltage range from 2.0 to 6.0 V
  • CMOS low power dissipation
  • High noise immunity
  • Input levels:
    • For 74HC74: CMOS level
    • For 74HCT74: TTL level
  • Symmetrical output impedance
  • High noise immunity
  • Balanced propagation delays
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
  • Complies with JEDEC standards:
    • JESD8C (2.7 V to 3.6 V)
    • JESD7A (2.0 V to 6.0 V)
Supplier's Site Datasheet
Thief River Falls, MN, United States
IC FF D-TYPE DUAL 1BIT 14DHXQFN

IC FF D-TYPE DUAL 1BIT 14DHXQFN

Supplier's Site Datasheet
Thief River Falls, MN, United States
IC FF D-TYPE DUAL 1BIT 14DHXQFN

IC FF D-TYPE DUAL 1BIT 14DHXQFN

Supplier's Site Datasheet
Thief River Falls, MN, United States
IC FF D-TYPE DUAL 1BIT 14DHXQFN

IC FF D-TYPE DUAL 1BIT 14DHXQFN

Supplier's Site Datasheet
Integrated Circuits (ICs) - Logic - Flip Flops - 74HCT74BZZ - Acme Chip Technology Co., Limited
Shenzhen, China
Integrated Circuits (ICs) - Logic - Flip Flops
74HCT74BZZ
Integrated Circuits (ICs) - Logic - Flip Flops 74HCT74BZZ
IC FF D-TYPE DUAL 1BIT 14DHXQFN

IC FF D-TYPE DUAL 1BIT 14DHXQFN

Supplier's Site
Flip Flops - 74HCT74BZZ - Quarktwin Technology Ltd.
Shenzhen, Guangdong, China
Flip Flops
74HCT74BZZ
Flip Flops 74HCT74BZZ
Flip Flop 2 Element D-Type 1 Bit Positive Edge 14-XFQFN Exposed Pad

Flip Flop 2 Element D-Type 1 Bit Positive Edge 14-XFQFN Exposed Pad

Supplier's Site

Technical Specifications

  Nexperia B.V. DigiKey Acme Chip Technology Co., Limited Quarktwin Technology Ltd.
Product Category Flip-Flops Flip-Flops Flip-Flops Flip-Flops
Product Number 74HCT74BZZ 1727-74HCT74BZZDKR-ND 74HCT74BZZ 74HCT74BZZ
Product Name Dual D-type flip-flop with set and reset; positive edge-trigger Flip Flops Integrated Circuits (ICs) - Logic - Flip Flops Flip Flops
Flip-Flop Type D D D
Triggering Positive-edge Triggered Positive-edge Triggered
Supply Voltage 5V; 4.5 - 5.5 4.5V ~ 5.5V 4.5V ~ 5.5V
Propagation Delay 15 ns 53 ns
fMAX 59 MHz
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