Nexperia B.V. Hex D-type flip-flop with reset; positive-edge trigger 74HCT174PW,112

Description
The 74HC174; 74HCT174 are hex positive edge-triggered D-type flip-flops with individual data inputs (Dn) and outputs (Qn). The common clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition is stored in the flip-flop and appears at the Q output. A LOW on MR causes the flip-flops and outputs to be reset LOW. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. Features and benefits Wide supply voltage range from 2.0 to 6.0 V CMOS low power dissipation High noise immunity Input levels: For 74HC174: CMOS level For 74HCT174: TTL level Six edge-triggered D-type flip-flops Asynchronous master reset Complies with JEDEC standards JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V) Latch-up performance exceeds 100 mA per JESD 78 Class II Level B ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Specified from -40 °C to +85 °C and -40 °C to +125 °C.
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Suppliers

Company
Product
Description
Supplier Links
Hex D-type flip-flop with reset; positive-edge trigger - 74HCT174PW,112 - Nexperia B.V.
Nijmegen, Netherlands
Hex D-type flip-flop with reset; positive-edge trigger
74HCT174PW,112
Hex D-type flip-flop with reset; positive-edge trigger 74HCT174PW,112
The 74HC174; 74HCT174 are hex positive edge-triggered D-type flip-flops with individual data inputs (Dn) and outputs (Qn). The common clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition is stored in the flip-flop and appears at the Q output. A LOW on MR causes the flip-flops and outputs to be reset LOW. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. Features and benefits Wide supply voltage range from 2.0 to 6.0 V CMOS low power dissipation High noise immunity Input levels: For 74HC174: CMOS level For 74HCT174: TTL level Six edge-triggered D-type flip-flops Asynchronous master reset Complies with JEDEC standards JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V) Latch-up performance exceeds 100 mA per JESD 78 Class II Level B ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Specified from -40 °C to +85 °C and -40 °C to +125 °C.

The 74HC174; 74HCT174 are hex positive edge-triggered D-type flip-flops with individual data inputs (Dn) and outputs (Qn). The common clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition is stored in the flip-flop and appears at the Q output. A LOW on MR causes the flip-flops and outputs to be reset LOW. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

Features and benefits

  • Wide supply voltage range from 2.0 to 6.0 V
  • CMOS low power dissipation
  • High noise immunity
  • Input levels:
    • For 74HC174: CMOS level
    • For 74HCT174: TTL level
  • Six edge-triggered D-type flip-flops
  • Asynchronous master reset
  • Complies with JEDEC standards
    • JESD8C (2.7 V to 3.6 V)
    • JESD7A (2.0 V to 6.0 V)
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
  • ESD protection:
    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C.
Supplier's Site Datasheet
Flip Flops - 74HCT174PW,112-ND - DigiKey
Thief River Falls, MN, United States
"Flip Flop 1 Element D-Type 6 Bit Positive Edge 16-TSSOP (0.173"", 4.40mm Width)"

"Flip Flop 1 Element D-Type 6 Bit Positive Edge 16-TSSOP (0.173"", 4.40mm Width)"

Buy Now Datasheet
Logic - Flip Flops - 74HCT174PW,112 - Nova Technology(HK) Co.,Ltd
Futian District, Shenzhen, China
Logic - Flip Flops
74HCT174PW,112
Logic - Flip Flops 74HCT174PW,112
Flip Flop 1 Element D-Type 6 Bit Positive Edge 16-TSSOP (0.173

Flip Flop 1 Element D-Type 6 Bit Positive Edge 16-TSSOP (0.173

Supplier's Site Datasheet
Flip Flops - 74HCT174PW,112 - Quarktwin Technology Ltd.
Shenzhen, Guangdong, China
Flip Flops
74HCT174PW,112
Flip Flops 74HCT174PW,112
Flip Flop 1 Element D-Type 6 Bit Positive Edge 16-TSSOP (0.173", 4.40mm Width)

Flip Flop 1 Element D-Type 6 Bit Positive Edge 16-TSSOP (0.173", 4.40mm Width)

Buy Now Datasheet
Integrated Circuits (ICs) - Logic - Flip Flops - 74HCT174PW,112 - Shenzhen Shengyu Electronics Technology Limited
Futian, China
Integrated Circuits (ICs) - Logic - Flip Flops
74HCT174PW,112
Integrated Circuits (ICs) - Logic - Flip Flops 74HCT174PW,112
IC FF D-TYPE SNGL 6BIT 16TSSOP

IC FF D-TYPE SNGL 6BIT 16TSSOP

Supplier's Site
Logic - Flip Flops - 74HCT174PW,112 - Lingto Electronic Limited
Shenzhen, China
Logic - Flip Flops
74HCT174PW,112
Logic - Flip Flops 74HCT174PW,112
IC FF D-TYPE SNGL 6BIT 16TSSOP

IC FF D-TYPE SNGL 6BIT 16TSSOP

Supplier's Site Datasheet

Technical Specifications

  Nexperia B.V. DigiKey Nova Technology(HK) Co.,Ltd Quarktwin Technology Ltd. Shenzhen Shengyu Electronics Technology Limited Lingto Electronic Limited
Product Category Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops
Product Number 74HCT174PW,112 74HCT174PW,112-ND 74HCT174PW,112 74HCT174PW,112 74HCT174PW,112 74HCT174PW,112
Product Name Hex D-type flip-flop with reset; positive-edge trigger Flip Flops Logic - Flip Flops Flip Flops Integrated Circuits (ICs) - Logic - Flip Flops Logic - Flip Flops
Flip-Flop Type D D D D
Triggering Positive-edge Triggered Positive-edge Triggered Positive-edge Triggered
Supply Voltage 5V; 4.5 - 5.5 4.5V ~ 5.5V 4.5V ~ 5.5V
Features ESD Protection
Propagation Delay 18 ns 35 ns
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