The 74HC4351; 74HCT4351 is a single-pole octal-throw analog switch (SP8T) suitable for use in analog or digital 8:1 multiplexer/demultip
lexer applications. The switch features three digital select inputs (S0 to S2), eight independent inputs/outputs (Yn), a common input/output (Z) and two digital enable inputs (E1 and E2). With E1 LOW and E2 HIGH, one of the eight switches is selected (low impedance ON-state) by S0 to S2. The data at the select inputs may be latched by using the latch enable input (LE). When LEis HIGH the latch is transparent. When E1 is HIGH or E2 is LOW all 8 analog switches are turned off. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
Features and benefits
Wide analog input voltage range from -5 V to +5 V
Complies with JEDEC standard no. 7A
Low ON resistance:
80 Ω (typical) at VCC - VEE = 4.5 V
70 Ω (typical) at VCC - VEE = 6.0 V
60 Ω (typical) at VCC - VEE = 9.0 V
Logic level translation: to enable 5 V logic to communicate with ±5 V analog signals
Typical ‘break before make’ built-in
Address latches provided
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Specified from -40 °C to +85 °C and -40 °C to +125 °C
Applications
Analog multiplexing and demultiplexing
Digital multiplexing and demultiplexing
Signal gating
The 74HC4351; 74HCT4351 is a single-pole octal-throw analog switch (SP8T) suitable for use in analog or digital 8:1 multiplexer/demultiplexer applications. The switch features three digital select inputs (S0 to S2), eight independent inputs/outputs (Yn), a common input/output (Z) and two digital enable inputs (E1 and E2). With E1 LOW and E2 HIGH, one of the eight switches is selected (low impedance ON-state) by S0 to S2. The data at the select inputs may be latched by using the latch enable input (LE). When LEis HIGH the latch is transparent. When E1 is HIGH or E2 is LOW all 8 analog switches are turned off. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
Features and benefits
- Wide analog input voltage range from -5 V to +5 V
- Complies with JEDEC standard no. 7A
- Low ON resistance:
- 80 Ω (typical) at VCC - VEE = 4.5 V
- 70 Ω (typical) at VCC - VEE = 6.0 V
- 60 Ω (typical) at VCC - VEE = 9.0 V
- Logic level translation: to enable 5 V logic to communicate with ±5 V analog signals
- Typical ‘break before make’ built-in
- Address latches provided
- ESD protection:
- HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
- CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
- Specified from -40 °C to +85 °C and -40 °C to +125 °C
Applications
- Analog multiplexing and demultiplexing
- Digital multiplexing and demultiplexing
- Signal gating
