Nexperia B.V. Quad D-type flip-flop; positive-edge trigger; 3-state 74HC173D,653

Description
The 74HC173; 74HCT173 is a quad positive-edge triggered D-type flip-flop. The device features clock (CP), master reset (MR), two input enable (E1, E2) and two output enable (OE1, OE2) inputs. When the input enables are LOW, the outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH on either input enable will cause the device to go into a hold mode, outputs hold their previous state independently of clock and data inputs. A HIGH on MR forces the outputs LOW independently of clock and data inputs. A HIGH on either output enable pin causes the outputs to assume a high-impedance OFF-state. Operation of the output enable inputs does not affect the state of the flip-flops. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. Features and benefits Complies with JEDEC standard no. 7A Input levels: For 74HC173: CMOS level For 74HCT173: TTL level Gated input enable for hold (do nothing) mode Gated output enable control mode Edge-triggered D-type register Asynchronous master reset ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Specified from -40 °C to +85 °C and -40 °C to +125 °C
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Description
The 74HC173; 74HCT173 is a quad positive-edge triggered D-type flip-flop. The device features clock (CP), master reset (MR), two input enable (E1, E2) and two output enable (OE1, OE2) inputs. When the input enables are LOW, the outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH on either input enable will cause the device to go into a hold mode, outputs hold their previous state independently of clock and data inputs. A HIGH on MR forces the outputs LOW independently of clock and data inputs. A HIGH on either output enable pin causes the outputs to assume a high-impedance OFF-state. Operation of the output enable inputs does not affect the state of the flip-flops. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. Features and benefits Complies with JEDEC standard no. 7A Input levels: For 74HC173: CMOS level For 74HCT173: TTL level Gated input enable for hold (do nothing) mode Gated output enable control mode Edge-triggered D-type register Asynchronous master reset ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Specified from -40 °C to +85 °C and -40 °C to +125 °C
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Quad D-type flip-flop; positive-edge trigger; 3-state - 74HC173D,653 - Nexperia B.V.
Nijmegen, Netherlands
Quad D-type flip-flop; positive-edge trigger; 3-state
74HC173D,653
Quad D-type flip-flop; positive-edge trigger; 3-state 74HC173D,653
The 74HC173; 74HCT173 is a quad positive-edge triggered D-type flip-flop. The device features clock (CP), master reset (MR), two input enable (E1, E2) and two output enable (OE1, OE2) inputs. When the input enables are LOW, the outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH on either input enable will cause the device to go into a hold mode, outputs hold their previous state independently of clock and data inputs. A HIGH on MR forces the outputs LOW independently of clock and data inputs. A HIGH on either output enable pin causes the outputs to assume a high-impedance OFF-state. Operation of the output enable inputs does not affect the state of the flip-flops. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. Features and benefits Complies with JEDEC standard no. 7A Input levels: For 74HC173: CMOS level For 74HCT173: TTL level Gated input enable for hold (do nothing) mode Gated output enable control mode Edge-triggered D-type register Asynchronous master reset ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Specified from -40 °C to +85 °C and -40 °C to +125 °C

The 74HC173; 74HCT173 is a quad positive-edge triggered D-type flip-flop. The device features clock (CP), master reset (MR), two input enable (E1, E2) and two output enable (OE1, OE2) inputs. When the input enables are LOW, the outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH on either input enable will cause the device to go into a hold mode, outputs hold their previous state independently of clock and data inputs. A HIGH on MR forces the outputs LOW independently of clock and data inputs. A HIGH on either output enable pin causes the outputs to assume a high-impedance OFF-state. Operation of the output enable inputs does not affect the state of the flip-flops. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

Features and benefits

  • Complies with JEDEC standard no. 7A
  • Input levels:
    • For 74HC173: CMOS level
    • For 74HCT173: TTL level
  • Gated input enable for hold (do nothing) mode
  • Gated output enable control mode
  • Edge-triggered D-type register
  • Asynchronous master reset
  • ESD protection:
    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C
Supplier's Site Datasheet
Laguna Hills, CA, United States
Logic - Logic - Flip Flops - 74HC173D,653
1008263-74HC173D,653
Logic - Logic - Flip Flops - 74HC173D,653 1008263-74HC173D,653
Manufacturer: Nexperia USA Inc. Win Source Part Number: 1008263-74HC173D,653 Packaging: Reel - TR Type: D-Type Mounting: SMD (SMT) Output Type: Tri-State, Non-Inverted Current - Output High, Low: 7.8mA, 7.8mA Number of Elements: 1 Number of Bits per Element: 4 Max Propagation Delay @ V, Max CL: 30ns @ 6V, 50pF Trigger Type: Positive Edge Current - Quiescent: 4μA Input Capacitance: 3.5pF Categories: Integrated Circuits Status: Active Temperature Range - Operating: -40°C to 125°C (TA) Dimension: 16-SOIC (0.154", 3.90mm Width) Purpose: Master Reset Supply Voltage - Operating: 2 V to 6 V Max Frequency: 95MHz Alternative Parts (Cross-Reference): CD74HC173M96; 74HC173D,652; 74HC173D; Popularity: Medium Fake Threat In the Open Market: 62 pct. Supply and Demand Status: Balance

Manufacturer: Nexperia USA Inc.
Win Source Part Number: 1008263-74HC173D,653
Packaging: Reel - TR
Type: D-Type
Mounting: SMD (SMT)
Output Type: Tri-State, Non-Inverted
Current - Output High, Low: 7.8mA, 7.8mA
Number of Elements: 1
Number of Bits per Element: 4
Max Propagation Delay @ V, Max CL: 30ns @ 6V, 50pF
Trigger Type: Positive Edge
Current - Quiescent: 4μA
Input Capacitance: 3.5pF
Categories: Integrated Circuits
Status: Active
Temperature Range - Operating: -40°C to 125°C (TA)
Dimension: 16-SOIC (0.154", 3.90mm Width)
Purpose: Master Reset
Supply Voltage - Operating: 2 V to 6 V
Max Frequency: 95MHz
Alternative Parts (Cross-Reference): CD74HC173M96; 74HC173D,652; 74HC173D;
Popularity: Medium
Fake Threat In the Open Market: 62 pct.
Supply and Demand Status: Balance

Buy Now Datasheet
Flip Flops - 1727-4067-1-ND - DigiKey
Thief River Falls, MN, United States
Flip Flops
1727-4067-1-ND
Flip Flops 1727-4067-1-ND
"Flip Flop 1 Element D-Type 4 Bit Positive Edge 16-SOIC (0.154"", 3.90mm Width)"

"Flip Flop 1 Element D-Type 4 Bit Positive Edge 16-SOIC (0.154"", 3.90mm Width)"

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Flip Flops - 1727-4067-6-ND - DigiKey
Thief River Falls, MN, United States
Flip Flops
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Flip Flops 1727-4067-6-ND
"Flip Flop 1 Element D-Type 4 Bit Positive Edge 16-SOIC (0.154"", 3.90mm Width)"

"Flip Flop 1 Element D-Type 4 Bit Positive Edge 16-SOIC (0.154"", 3.90mm Width)"

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Flip Flops - 1727-4067-2-ND - DigiKey
Thief River Falls, MN, United States
Flip Flops
1727-4067-2-ND
Flip Flops 1727-4067-2-ND
"Flip Flop 1 Element D-Type 4 Bit Positive Edge 16-SOIC (0.154"", 3.90mm Width)"

"Flip Flop 1 Element D-Type 4 Bit Positive Edge 16-SOIC (0.154"", 3.90mm Width)"

Buy Now Datasheet
Integrated Circuits (ICs) - Logic - Flip Flops - 74HC173D,653 - Shenzhen Shengyu Electronics Technology Limited
Futian, China
Integrated Circuits (ICs) - Logic - Flip Flops
74HC173D,653
Integrated Circuits (ICs) - Logic - Flip Flops 74HC173D,653
IC FF D-TYPE SNGL 4BIT 16SO

IC FF D-TYPE SNGL 4BIT 16SO

Supplier's Site
Flip Flop, D, -40 To 125Deg C Rohs Compliant Nexperia - 74AH2422 - Newark, An Avnet Company
Chicago, IL, United States
Flip Flop, D, -40 To 125Deg C Rohs Compliant Nexperia
74AH2422
Flip Flop, D, -40 To 125Deg C Rohs Compliant Nexperia 74AH2422
FLIP FLOP, D, -40 TO 125DEG C ROHS COMPLIANT: YES

FLIP FLOP, D, -40 TO 125DEG C ROHS COMPLIANT: YES

Supplier's Site Datasheet
Logic - Flip Flops - 74HC173D,653 - Lingto Electronic Limited
Shenzhen, China
Logic - Flip Flops
74HC173D,653
Logic - Flip Flops 74HC173D,653
IC FF D-TYPE SNGL 4BIT 16SO

IC FF D-TYPE SNGL 4BIT 16SO

Supplier's Site Datasheet
IC FF D-TYPE SNGL 4BIT 16SO - 554-74HC173D,653 - Utmel Electronic Limited
Hong Kong, China
IC FF D-TYPE SNGL 4BIT 16SO
554-74HC173D,653
IC FF D-TYPE SNGL 4BIT 16SO 554-74HC173D,653
IC FF D-TYPE SNGL 4BIT 16SO

IC FF D-TYPE SNGL 4BIT 16SO

Supplier's Site
Flip Flops - 74HC173D,653 - Quarktwin Technology Ltd.
Shenzhen, Guangdong, China
Flip Flops
74HC173D,653
Flip Flops 74HC173D,653
Flip Flop 1 Element D-Type 4 Bit Positive Edge 16-SOIC (0.154", 3.90mm Width)

Flip Flop 1 Element D-Type 4 Bit Positive Edge 16-SOIC (0.154", 3.90mm Width)

Buy Now Datasheet

Technical Specifications

  Nexperia B.V. Win Source Electronics DigiKey Shenzhen Shengyu Electronics Technology Limited Newark, An Avnet Company Lingto Electronic Limited Utmel Electronic Limited Quarktwin Technology Ltd.
Product Category Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops
Product Number 74HC173D,653 1008263-74HC173D,653 1727-4067-1-ND 74HC173D,653 74AH2422 74HC173D,653 554-74HC173D,653 74HC173D,653
Product Name Quad D-type flip-flop; positive-edge trigger; 3-state Logic - Logic - Flip Flops - 74HC173D,653 Flip Flops Integrated Circuits (ICs) - Logic - Flip Flops Flip Flop, D, -40 To 125Deg C Rohs Compliant Nexperia Logic - Flip Flops IC FF D-TYPE SNGL 4BIT 16SO Flip Flops
Flip-Flop Type D D D D
Triggering Positive-edge Triggered Positive-edge Triggered; Positive Edge Positive-edge Triggered Positive-edge Triggered
Supply Voltage +7.0 2 V ~ 6 V 2V ~ 6V 5V; 2V~6V 2V ~ 6V
Output Characteristics 3-State 3-State
Features ESD Protection
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