Nexperia B.V. Presettable synchronous 4-bit binary counter; asynchronous reset 74HC161PW,118

Description
The 74HC161 is a synchronous presettable binary counter with an internal look-head carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset HIGH or LOW. A LOW at the parallel enable input (PE) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock. Preset takes place regardless of the levels at count enable inputs (CEP and CET). A LOW at the master reset input (MR) sets Q0 to Q3 LOW regardless of the levels at input pins CP, PE, CET and CEP (thus providing an asynchronous clear function). The look-ahead carry simplifies serial cascading of the counters. Both CEP and CET must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH output of Q0. This pulse can be used to enable the next cascaded stage. The maximum clock frequency for the cascaded counters is determined by the CP to TC propagation delay and CEP to CP set-up time, according to the following formula: Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. Features and benefits Wide supply voltage range from 2.0 V to 6.0 V CMOS low power dissipation High noise immunity Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Complies with JEDEC standards: JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V) CMOS input levels Synchronous counting and loading 2 count enable inputs for n-bit cascading Asynchronous reset Positive-edge triggered clock ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Specified from -40 °C to +85 °C and -40 °C to +125 °C
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Description
The 74HC161 is a synchronous presettable binary counter with an internal look-head carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset HIGH or LOW. A LOW at the parallel enable input (PE) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock. Preset takes place regardless of the levels at count enable inputs (CEP and CET). A LOW at the master reset input (MR) sets Q0 to Q3 LOW regardless of the levels at input pins CP, PE, CET and CEP (thus providing an asynchronous clear function). The look-ahead carry simplifies serial cascading of the counters. Both CEP and CET must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH output of Q0. This pulse can be used to enable the next cascaded stage. The maximum clock frequency for the cascaded counters is determined by the CP to TC propagation delay and CEP to CP set-up time, according to the following formula: Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. Features and benefits Wide supply voltage range from 2.0 V to 6.0 V CMOS low power dissipation High noise immunity Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Complies with JEDEC standards: JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V) CMOS input levels Synchronous counting and loading 2 count enable inputs for n-bit cascading Asynchronous reset Positive-edge triggered clock ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Specified from -40 °C to +85 °C and -40 °C to +125 °C
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Suppliers

Company
Product
Description
Supplier Links
Presettable synchronous 4-bit binary counter; asynchronous reset - 74HC161PW,118 - Nexperia B.V.
Nijmegen, Netherlands
Presettable synchronous 4-bit binary counter; asynchronous reset
74HC161PW,118
Presettable synchronous 4-bit binary counter; asynchronous reset 74HC161PW,118
The 74HC161 is a synchronous presettable binary counter with an internal look-head carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset HIGH or LOW. A LOW at the parallel enable input (PE) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock. Preset takes place regardless of the levels at count enable inputs (CEP and CET). A LOW at the master reset input (MR) sets Q0 to Q3 LOW regardless of the levels at input pins CP, PE, CET and CEP (thus providing an asynchronous clear function). The look-ahead carry simplifies serial cascading of the counters. Both CEP and CET must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH output of Q0. This pulse can be used to enable the next cascaded stage. The maximum clock frequency for the cascaded counters is determined by the CP to TC propagation delay and CEP to CP set-up time, according to the following formula: Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. Features and benefits Wide supply voltage range from 2.0 V to 6.0 V CMOS low power dissipation High noise immunity Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Complies with JEDEC standards: JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V) CMOS input levels Synchronous counting and loading 2 count enable inputs for n-bit cascading Asynchronous reset Positive-edge triggered clock ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Specified from -40 °C to +85 °C and -40 °C to +125 °C

The 74HC161 is a synchronous presettable binary counter with an internal look-head carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset HIGH or LOW. A LOW at the parallel enable input (PE) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock. Preset takes place regardless of the levels at count enable inputs (CEP and CET). A LOW at the master reset input (MR) sets Q0 to Q3 LOW regardless of the levels at input pins CP, PE, CET and CEP (thus providing an asynchronous clear function). The look-ahead carry simplifies serial cascading of the counters. Both CEP and CET must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH output of Q0. This pulse can be used to enable the next cascaded stage. The maximum clock frequency for the cascaded counters is determined by the CP to TC propagation delay and CEP to CP set-up time, according to the following formula:

Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

Features and benefits

  • Wide supply voltage range from 2.0 V to 6.0 V
  • CMOS low power dissipation
  • High noise immunity
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
  • Complies with JEDEC standards:
    • JESD8C (2.7 V to 3.6 V)
    • JESD7A (2.0 V to 6.0 V)
  • CMOS input levels
  • Synchronous counting and loading
  • 2 count enable inputs for n-bit cascading
  • Asynchronous reset
  • Positive-edge triggered clock
  • ESD protection:
    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C
Supplier's Site Datasheet
Counters, Dividers - 1727-6585-2-ND - DigiKey
Thief River Falls, MN, United States
Counters, Dividers
1727-6585-2-ND
Counters, Dividers 1727-6585-2-ND
Counter IC Binary Counter 1 Element 4 Bit Positive Edge 16-TSSOP

Counter IC Binary Counter 1 Element 4 Bit Positive Edge 16-TSSOP

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Counters, Dividers - 1727-6585-1-ND - DigiKey
Thief River Falls, MN, United States
Counters, Dividers
1727-6585-1-ND
Counters, Dividers 1727-6585-1-ND
Counter IC Binary Counter 1 Element 4 Bit Positive Edge 16-TSSOP

Counter IC Binary Counter 1 Element 4 Bit Positive Edge 16-TSSOP

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Counters, Dividers - 1727-6585-6-ND - DigiKey
Thief River Falls, MN, United States
Counters, Dividers
1727-6585-6-ND
Counters, Dividers 1727-6585-6-ND
Counter IC Binary Counter 1 Element 4 Bit Positive Edge 16-TSSOP

Counter IC Binary Counter 1 Element 4 Bit Positive Edge 16-TSSOP

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 - 74HC161PW,118 - Rochester Electronics
Newburyport, MA, United States
Binary Counter, HC/UH Series, Synchronous, Positive Edge Triggered, 4-Bit, Up Direction, CMOS, PDSO16

Binary Counter, HC/UH Series, Synchronous, Positive Edge Triggered, 4-Bit, Up Direction, CMOS, PDSO16

Supplier's Site Datasheet
Logic - Logic - Counters, Dividers - 74HC161PW,118 - 1008247-74HC161PW,118 - Win Source Electronics
Laguna Hills, CA, United States
Logic - Logic - Counters, Dividers - 74HC161PW,118
1008247-74HC161PW,118
Logic - Logic - Counters, Dividers - 74HC161PW,118 1008247-74HC161PW,118
Manufacturer: Nexperia USA Inc. Win Source Part Number: 1008247-74HC161PW,11 8 Packaging: Reel - TR Mounting: SMD (SMT) Logic Type: Binary Counter Number of Elements: 1 Number of Bits per Element: 4 Trigger Type: Positive Edge Direction: Up Reset: Asynchronous Timing: Asynchronous/Synchro nous Count Rate: 48MHz Categories: Integrated Circuits Status: Active Temperature Range - Operating: -40°C to 125°C Case / Package: 16-TSSOP Supply Voltage - Operating: 2 V to 6 V Popularity: Medium Fake Threat In the Open Market: 41 pct. Supply and Demand Status: Balance

Manufacturer: Nexperia USA Inc.
Win Source Part Number: 1008247-74HC161PW,118
Packaging: Reel - TR
Mounting: SMD (SMT)
Logic Type: Binary Counter
Number of Elements: 1
Number of Bits per Element: 4
Trigger Type: Positive Edge
Direction: Up
Reset: Asynchronous
Timing: Asynchronous/Synchronous
Count Rate: 48MHz
Categories: Integrated Circuits
Status: Active
Temperature Range - Operating: -40°C to 125°C
Case / Package: 16-TSSOP
Supply Voltage - Operating: 2 V to 6 V
Popularity: Medium
Fake Threat In the Open Market: 41 pct.
Supply and Demand Status: Balance

Buy Now Datasheet
Integrated Circuits (ICs) - Logic - Counters, Dividers - 74HC161PW,118 - Shenzhen Shengyu Electronics Technology Limited
Futian, China
Integrated Circuits (ICs) - Logic - Counters, Dividers
74HC161PW,118
Integrated Circuits (ICs) - Logic - Counters, Dividers 74HC161PW,118
IC BINARY COUNTER 4-BIT 16TSSOP

IC BINARY COUNTER 4-BIT 16TSSOP

Supplier's Site
Binary Counter, 4Bit, 44Mhz, Tssop-16; Logic Family / Base Number Nexperia - 85X2887 - Newark, An Avnet Company
Chicago, IL, United States
Binary Counter, 4Bit, 44Mhz, Tssop-16; Logic Family / Base Number Nexperia
85X2887
Binary Counter, 4Bit, 44Mhz, Tssop-16; Logic Family / Base Number Nexperia 85X2887
BINARY COUNTER, 4BIT, 44MHZ, TSSOP-16; Logic Family / Base Number:74HC161; Counter Type:Binary; Clock Frequency:44MHz; Count Maximum:15; Logic Case Style:TSSOP; No. of Pins:16Pins; Supply Voltage Min:2V; Supply Voltage Max:6V; Logic RoHS Compliant: Yes

BINARY COUNTER, 4BIT, 44MHZ, TSSOP-16; Logic Family / Base Number:74HC161; Counter Type:Binary; Clock Frequency:44MHz; Count Maximum:15; Logic Case Style:TSSOP; No. of Pins:16Pins; Supply Voltage Min:2V; Supply Voltage Max:6V; Logic RoHS Compliant: Yes

Supplier's Site Datasheet
Logic - Counters, Dividers - 74HC161PW,118 - Lingto Electronic Limited
Shenzhen, China
Logic - Counters, Dividers
74HC161PW,118
Logic - Counters, Dividers 74HC161PW,118
IC SYNC 4BIT BINAR COUNT 16TSSOP

IC SYNC 4BIT BINAR COUNT 16TSSOP

Supplier's Site Datasheet
Counters, Dividers - 74HC161PW,118 - Quarktwin Technology Ltd.
Shenzhen, Guangdong, China
Counters, Dividers
74HC161PW,118
Counters, Dividers 74HC161PW,118
Counter IC Binary Counter 1 Element 4 Bit Positive Edge 16-TSSOP

Counter IC Binary Counter 1 Element 4 Bit Positive Edge 16-TSSOP

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Technical Specifications

  Nexperia B.V. DigiKey Rochester Electronics Win Source Electronics Shenzhen Shengyu Electronics Technology Limited Newark, An Avnet Company Lingto Electronic Limited Quarktwin Technology Ltd.
Product Category Logic Counters Logic Counters Logic Counters Logic Counters Logic Counters Logic Counters Logic Counters Logic Counters
Product Number 74HC161PW,118 1727-6585-2-ND 74HC161PW,118 1008247-74HC161PW,118 74HC161PW,118 85X2887 74HC161PW,118 74HC161PW,118
Product Name Presettable synchronous 4-bit binary counter; asynchronous reset Counters, Dividers Logic - Logic - Counters, Dividers - 74HC161PW,118 Integrated Circuits (ICs) - Logic - Counters, Dividers Binary Counter, 4Bit, 44Mhz, Tssop-16; Logic Family / Base Number Nexperia Logic - Counters, Dividers Counters, Dividers
Features ESD Protection
Counter Category Synchronous; Asynchronous Synchronous; Asynchronous Synchronous Synchronous
Supply Voltage +7.0 2 V ~ 6 V 2V 2 V ~ 6 V
Package Type SOT403-1 SOT403-1 TSSOP; "16-TSSOP (0.173"", 4.40mm Width)" SOT403 SOP; SSOP; TSSOP; 16-TSSOP SSOP TSSOP SOP; SSOP; TSSOP; 16-TSSOP (0.173\", 4.40mm Width)
Operating Temperature 125 C (257 F) -40 to 125 C (-40 to 257 F) -40 to 125 C (-40 to 257 F) -40 to 125 C (-40 to 257 F) -40 to 125 C (-40 to 257 F)
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