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Nexperia B.V. 18-bit bus-interface D-type flip-flop with reset and enable; 3-state 74ALVCH16823DGGS

Description
The 74ALVCH16823 is an 18-bit edge-triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. Incorporates bushold data inputs which eliminate the need for external pull-up resistors to hold unused inputs. The 74ALVCH16823 consists of two sections of nine edge-triggered flip-flops. A clock (nCP) input, an output-enable (nOE) input, a master reset (nMR) input and a clock-enable (nCE) input are provided for each total 9-bit section. With the clock-enable (nCE) input LOW, the D-type flip-flops will store the state of their individual nDn-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH nCP transition. Taking nCE HIGH disables the clock buffer, thus latching the outputs. Taking the master reset (nMR) input LOW causes all the nQn outputs to go LOW independently of the clock. When nOE is LOW, the contents of the flip-flops are available at the outputs. When the nOE is HIGH, the outputs go to the high impedance OFF-state. Operation of the nOE input does not affect the state of flip-flops. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Features and benefits Wide supply voltage range from 1.2 V to 3.6 V CMOS low-power consumption Direct interface with TTL levels Current drive ± 24 mA at 3.0 V MULTIBYTE™ flow-through standard pin-out architecture Low inductance multiple VCC and GND pins for minimum noise and ground bounce Output drive capability 50 Ω transmission lines at 85°C All data inputs have bushold Complies with JEDEC standard no. 8-1A Complies with JEDEC standards: JESD8-5 (2.3 V to 2.7 V) JESD8B/JESD36 (2.7 V to 3.6 V) ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Specified from -40 °C to +85 °C
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Suppliers

Company
Product
Description
Supplier Links
18-bit bus-interface D-type flip-flop with reset and enable; 3-state - 74ALVCH16823DGGS - Nexperia B.V.
Nijmegen, Netherlands
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
74ALVCH16823DGGS
18-bit bus-interface D-type flip-flop with reset and enable; 3-state 74ALVCH16823DGGS
The 74ALVCH16823 is an 18-bit edge-triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. Incorporates bushold data inputs which eliminate the need for external pull-up resistors to hold unused inputs. The 74ALVCH16823 consists of two sections of nine edge-triggered flip-flops. A clock (nCP) input, an output-enable (nOE) input, a master reset (nMR) input and a clock-enable (nCE) input are provided for each total 9-bit section. With the clock-enable (nCE) input LOW, the D-type flip-flops will store the state of their individual nDn-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH nCP transition. Taking nCE HIGH disables the clock buffer, thus latching the outputs. Taking the master reset (nMR) input LOW causes all the nQn outputs to go LOW independently of the clock. When nOE is LOW, the contents of the flip-flops are available at the outputs. When the nOE is HIGH, the outputs go to the high impedance OFF-state. Operation of the nOE input does not affect the state of flip-flops. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Features and benefits Wide supply voltage range from 1.2 V to 3.6 V CMOS low-power consumption Direct interface with TTL levels Current drive ± 24 mA at 3.0 V MULTIBYTE™ flow-through standard pin-out architecture Low inductance multiple VCC and GND pins for minimum noise and ground bounce Output drive capability 50 Ω transmission lines at 85°C All data inputs have bushold Complies with JEDEC standard no. 8-1A Complies with JEDEC standards: JESD8-5 (2.3 V to 2.7 V) JESD8B/JESD36 (2.7 V to 3.6 V) ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Specified from -40 °C to +85 °C

The 74ALVCH16823 is an 18-bit edge-triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. Incorporates bushold data inputs which eliminate the need for external pull-up resistors to hold unused inputs. The 74ALVCH16823 consists of two sections of nine edge-triggered flip-flops. A clock (nCP) input, an output-enable (nOE) input, a master reset (nMR) input and a clock-enable (nCE) input are provided for each total 9-bit section.

With the clock-enable (nCE) input LOW, the D-type flip-flops will store the state of their individual nDn-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH nCP transition. Taking nCE HIGH disables the clock buffer, thus latching the outputs. Taking the master reset (nMR) input LOW causes all the nQn outputs to go LOW independently of the clock.

When nOE is LOW, the contents of the flip-flops are available at the outputs. When the nOE is HIGH, the outputs go to the high impedance OFF-state. Operation of the nOE input does not affect the state of flip-flops.

Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

Features and benefits

  • Wide supply voltage range from 1.2 V to 3.6 V
  • CMOS low-power consumption
  • Direct interface with TTL levels
  • Current drive ± 24 mA at 3.0 V
  • MULTIBYTE™ flow-through standard pin-out architecture
  • Low inductance multiple VCC and GND pins for minimum noise and ground bounce
  • Output drive capability 50 Ω transmission lines at 85°C
  • All data inputs have bushold
  • Complies with JEDEC standard no. 8-1A
  • Complies with JEDEC standards:
    • JESD8-5 (2.3 V to 2.7 V)
    • JESD8B/JESD36 (2.7 V to 3.6 V)
  • ESD protection:
    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
  • Specified from -40 °C to +85 °C
Supplier's Site Datasheet
Flip Flops - 74ALVCH16823DGGS - Quarktwin Technology Ltd.
Shenzhen, Guangdong, China
Flip Flop 2 Element D-Type 9 Bit Positive Edge 56-TFSOP (0.240", 6.10mm Width)

Flip Flop 2 Element D-Type 9 Bit Positive Edge 56-TFSOP (0.240", 6.10mm Width)

Supplier's Site Datasheet
Flip Flops - 1727-2441-ND - DigiKey
Thief River Falls, MN, United States
Flip Flops
1727-2441-ND
Flip Flops 1727-2441-ND
"Flip Flop 2 Element D-Type 9 Bit Positive Edge 56-TFSOP (0.240"", 6.10mm Width)"

"Flip Flop 2 Element D-Type 9 Bit Positive Edge 56-TFSOP (0.240"", 6.10mm Width)"

Supplier's Site Datasheet
Logic - Flip Flops - 74ALVCH16823DGGS - Lingto Electronic Limited
Shenzhen, China
Logic - Flip Flops
74ALVCH16823DGGS
Logic - Flip Flops 74ALVCH16823DGGS
IC FF D-TYPE DUAL 9BIT 56TSSOP

IC FF D-TYPE DUAL 9BIT 56TSSOP

Supplier's Site Datasheet

Technical Specifications

  Nexperia B.V. Quarktwin Technology Ltd. DigiKey Lingto Electronic Limited
Product Category Flip-Flops Flip-Flops Flip-Flops Flip-Flops
Product Number 74ALVCH16823DGGS 74ALVCH16823DGGS 1727-2441-ND 74ALVCH16823DGGS
Product Name 18-bit bus-interface D-type flip-flop with reset and enable; 3-state Flip Flops Flip Flops Logic - Flip Flops
Flip-Flop Type D D D
Supply Voltage 1.2V; 1.5V; 1.8V; 2.5V; 3V; 3.3V; 3.6V; 1.2 - 3.6 3V; 3.6V; 2.3V ~ 2.7V, 3V ~ 3.6V 2.3V ~ 2.7V, 3V ~ 3.6V
Output Characteristics 3-State; OE 3-State
Features ESD Protection
Propagation Delay 2.1 ns 3.7 ns
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