Nexperia B.V. 18-bit universal bus transceiver; 3-state 74ALVCH16601DGGY

The 74ALVCH16601 is an 18-bit universal transceiver with bus hold inputs and 3-state outputs. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), clock enable (CEAB and CEBA) and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CPAB is held at a HIGH or LOW logic level. If LEAB and CEAB are LOW, the A-bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CPAB. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the outputs are in the high-impedance state. Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA, CEBA and CPBA. This device is fully specified for partial power down applications using I_OFF. The I_OFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Features and benefits

• Wide supply voltage range from 1.65 V to 3.6 V
• CMOS low power dissipation
• MULTIBYTE™ flow-through standard pin-out architecture
• Low inductance multiple V_CC and GND pins for minimum noise and ground bounce
• Direct interface with TTL levels
• Bus hold on data inputs
• Output drive capability 50 Ω transmission lines at 85 °C
• Current drive ±24 mA at 3.0 V
• Latch-up performance exceeds 100 mA per JESD 78 Class II Leve B
• Complies with JEDEC standards:
• JESD8-7 (1.65 V to 1.95 V)
• JESD8-5 (2.3 V to 2.7 V)
• JESD8C (2.7 V to 3.6 V)
• ESD protection:
• HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
• CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C

Universal Bus Transceiver 18-Bit 56-TSSOP

IC UNIV BUS TXRX 18BIT 56TSSOP

IC UNIV BUS TXRX 18BIT 56TSSOP

Universal Bus Transceiver 18-Bit 56-TSSOP

Universal Bus Transceiver 18-Bit 56-TSSOP