Nexperia B.V. Octal D-type flip-flop; positive edge-trigger; 3-state 74ALVC574D,118

Description
The 74ALVC574 is an 8-bit positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. Schmitt trigger action on all inputs makes the device tolerant of slow rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. Features and benefits Wide supply voltage range from 1.65 V to 3.6 V CMOS low power dissipation Overvoltage tolerant inputs to 3.6 V Direct interface with TTL levels IOFF circuitry provides partial Power-down mode operation Latch-up performance exceeds 250 mA per JESD78 Class II.A Complies with JEDEC standards: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Multiple package options Specified from -40 °C to +85 °C and from -40 °C to +125 °C
  • Octal D-type flip-flop; positive edge-trigger; 3-state - 74ALVC574D,118 - Nexperia B.V.
    Nexperia B.V.
  • Flip Flops - 1727-74ALVC574D,118TR-ND - DigiKey
    DigiKey
  • Integrated Circuits (ICs) - Logic - Flip Flops - 74ALVC574D,118 - Shenzhen Shengyu Electronics Technology Limited
    Shenzhen Shengyu Electronics Technology Limited
  • Logic - Flip Flops - 74ALVC574D,118 - Lingto Electronic Limited
    Lingto Electronic Limited
  • Flip Flops - 74ALVC574D,118 - Quarktwin Technology Ltd.
    Quarktwin Technology Ltd.
  • Flip Flop, D, -40 To 85Deg C Rohs Compliant Nexperia - 74AH2238 - Newark, An Avnet Company
    Newark, An Avnet Company
Request a Quote Datasheet
Description
The 74ALVC574 is an 8-bit positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. Schmitt trigger action on all inputs makes the device tolerant of slow rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. Features and benefits Wide supply voltage range from 1.65 V to 3.6 V CMOS low power dissipation Overvoltage tolerant inputs to 3.6 V Direct interface with TTL levels IOFF circuitry provides partial Power-down mode operation Latch-up performance exceeds 250 mA per JESD78 Class II.A Complies with JEDEC standards: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Multiple package options Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Request a Quote Datasheet

Suppliers

Company
Product
Description
Supplier Links
Octal D-type flip-flop; positive edge-trigger; 3-state - 74ALVC574D,118 - Nexperia B.V.
Nexperia B.V.
Nijmegen, Netherlands
Octal D-type flip-flop; positive edge-trigger; 3-state
74ALVC574D,118
Octal D-type flip-flop; positive edge-trigger; 3-state 74ALVC574D,118
The 74ALVC574 is an 8-bit positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. Schmitt trigger action on all inputs makes the device tolerant of slow rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. Features and benefits Wide supply voltage range from 1.65 V to 3.6 V CMOS low power dissipation Overvoltage tolerant inputs to 3.6 V Direct interface with TTL levels IOFF circuitry provides partial Power-down mode operation Latch-up performance exceeds 250 mA per JESD78 Class II.A Complies with JEDEC standards: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Multiple package options Specified from -40 °C to +85 °C and from -40 °C to +125 °C

The 74ALVC574 is an 8-bit positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops.

Schmitt trigger action on all inputs makes the device tolerant of slow rise and fall times.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Features and benefits

  • Wide supply voltage range from 1.65 V to 3.6 V
  • CMOS low power dissipation
  • Overvoltage tolerant inputs to 3.6 V
  • Direct interface with TTL levels
  • IOFF circuitry provides partial Power-down mode operation
  • Latch-up performance exceeds 250 mA per JESD78 Class II.A
  • Complies with JEDEC standards:
    • JESD8-7 (1.65 V to 1.95 V)
    • JESD8-5 (2.3 V to 2.7 V)
    • JESD8C/JESD36 (2.7 V to 3.6 V)
  • ESD protection:
    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
  • Multiple package options
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Supplier's Site Datasheet
Flip Flops - 1727-74ALVC574D,118TR-ND - DigiKey
DigiKey
Thief River Falls, MN, United States
Flip Flops
1727-74ALVC574D,118TR-ND
Flip Flops 1727-74ALVC574D,118TR-ND
"Flip Flop 1 Element D-Type 8 Bit Positive Edge 20-SOIC (0.295"", 7.50mm Width)"

"Flip Flop 1 Element D-Type 8 Bit Positive Edge 20-SOIC (0.295"", 7.50mm Width)"

Buy Now Datasheet
Integrated Circuits (ICs) - Logic - Flip Flops - 74ALVC574D,118 - Shenzhen Shengyu Electronics Technology Limited
Shenzhen Shengyu Electronics Technology Limited
Futian, China
Integrated Circuits (ICs) - Logic - Flip Flops
74ALVC574D,118
Integrated Circuits (ICs) - Logic - Flip Flops 74ALVC574D,118
IC FF D-TYPE SNGL 8BIT 20SO

IC FF D-TYPE SNGL 8BIT 20SO

Supplier's Site
Logic - Flip Flops - 74ALVC574D,118 - Lingto Electronic Limited
Lingto Electronic Limited
Shenzhen, China
Logic - Flip Flops
74ALVC574D,118
Logic - Flip Flops 74ALVC574D,118
IC FF D-TYPE SNGL 8BIT 20SO

IC FF D-TYPE SNGL 8BIT 20SO

Supplier's Site Datasheet
Flip Flops - 74ALVC574D,118 - Quarktwin Technology Ltd.
Quarktwin Technology Ltd.
Shenzhen, Guangdong, China
Flip Flops
74ALVC574D,118
Flip Flops 74ALVC574D,118
Flip Flop 1 Element D-Type 8 Bit Positive Edge 20-SOIC (0.295", 7.50mm Width)

Flip Flop 1 Element D-Type 8 Bit Positive Edge 20-SOIC (0.295", 7.50mm Width)

Buy Now Datasheet
Flip Flop, D, -40 To 85Deg C Rohs Compliant Nexperia - 74AH2238 - Newark, An Avnet Company
Newark, An Avnet Company
Chicago, IL, United States
Flip Flop, D, -40 To 85Deg C Rohs Compliant Nexperia
74AH2238
Flip Flop, D, -40 To 85Deg C Rohs Compliant Nexperia 74AH2238
FLIP FLOP, D, -40 TO 85DEG C ROHS COMPLIANT: YES

FLIP FLOP, D, -40 TO 85DEG C ROHS COMPLIANT: YES

Supplier's Site Datasheet

Technical Specifications

  Nexperia B.V. DigiKey Shenzhen Shengyu Electronics Technology Limited Lingto Electronic Limited Quarktwin Technology Ltd. Newark, An Avnet Company
Product Category Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops
Product Number 74ALVC574D,118 1727-74ALVC574D,118TR-ND 74ALVC574D,118 74ALVC574D,118 74ALVC574D,118 74AH2238
Product Name Octal D-type flip-flop; positive edge-trigger; 3-state Flip Flops Integrated Circuits (ICs) - Logic - Flip Flops Logic - Flip Flops Flip Flops Flip Flop, D, -40 To 85Deg C Rohs Compliant Nexperia
Flip-Flop Type D D D
Triggering Positive-edge Triggered Positive-edge Triggered
Supply Voltage 1.8V; 2.5V; 3V; 3.3V; 3.6V; 1.65 - 3.6 1.65V ~ 3.6V 3.6V; 1.65V ~ 3.6V
Output Characteristics 3-State 3-State
Features ESD Protection
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