Nexperia B.V. Octal D-type flip-flop; positive-edge trigger; 3-state 74ALVC374BQ,115

The 74ALVC374 is an octal positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH on OEcauses the outputs to assume a high-impedance OFF-state. Operation of the OEinput does not affect the state of the flip-flops.

Schmitt trigger action on all inputs makes the device tolerant of slow rise and fall times.

This device is fully specified for partial power down applications using I_OFF. The I_OFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Features and benefits

• Wide supply voltage range from 1.65 V to 3.6 V
• CMOS low power dissipation
• Overvoltage tolerant inputs to 3.6 V
• Direct interface with TTL levels
• I_OFF circuitry provides partial Power-down mode operation
• Latch-up performance exceeds 250 mA per JESD78 Class II.A
• Complies with JEDEC standards:
• JESD8-7 (1.65 V to 1.95 V)
• JESD8-5 (2.3 V to 2.7 V)
• JESD8C/JESD36 (2.7 V to 3.6 V)
• ESD protection:
• HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
• CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
• Multiple package options
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C

Flip Flop 1 Element D-Type 8 Bit Positive Edge 20-VFQFN Exposed Pad