Nexperia B.V. Dual D-type flip-flop with set and reset; positive-edge trigger 74AHC74D-Q100J

The 74AHC74-Q100; 74AHCT74-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A.

The 74AHC74-Q100; 74AHCT74-Q100 is a dual positive-edge triggered, D-type flip-flop with individual data inputs (D), clock inputs (CP), set inputs (SD) and reset inputs (RD). It also has complementary outputs (Q and Q).

The set and reset are asynchronous active LOW inputs that operate independent of the clock input. Information on the data input is transferred to the Q output on the LOW to HIGH transition of the clock pulse. The data inputs must be stable one set-up time prior to the LOW to HIGH clock transition for predictable operation.

Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

Features and benefits

• Automotive product qualification in accordance with AEC-Q100 (Grade 1)
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C
• Balanced propagation delays
• All inputs have Schmitt-trigger actions
• Inputs accept voltages higher than V_CC
• Input levels:
• For 74AHC74-Q100: CMOS level
• For 74AHCT74-Q100: TTL level
• ESD protection:
• HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
• CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
• Multiple package options
• DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints

"Flip Flop 2 Element D-Type 1 Bit Positive Edge 14-SOIC (0.154"", 3.90mm Width)"

D Flip-Flop, AHC/VHC/H/U/V Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS, PDSO14