The ZL30161 is a single channel Network Synchronization Clock Translator combining a single DPLL / NCO with three programmable synthesizers. The device is a fully compliant SEC (G.813) and EEC (G.8262) flexible rate conversion DPLL. It is capable of accepting and generating any frequency from 1Hz to 750MHz on up to eleven input references and up to twelve output clocks.
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Additional Features
Fully compliant SEC (G.813), EEC (G.8262) and Stratum 3E flexible rate conversion digital phase locked loop (DPLL)
Programmable DPLL/Numerically Controlled Oscillators (NCO)
Synchronizes to any clock rate from 1 Hz to 750 MHz
Three programmable synthesizers generate any clock rate from 1 Hz to 750 MHz with maximum jitter below 0.62 ps rms
Flexible two-stage architecture translates between arbitrary data rates, line coding rates and FEC rates
Digital PLL filters jitter from 0.1 mHz up to 1 kHz
Automatic hitless reference switching and digital holdover on reference fail
Nine input references configurable as single ended or differential and two single ended input references
Any input reference can be fed with sync (frame pulse) or clock
Programmable DPLL can synchronize to sync pulse and sync/clock pair.
Six LVPECL outputs and six LVCMOS outputs
Operates from a single crystal resonator or clock oscillator
Customer defined default device configuration available via OTP (One Time Programmable) memory, including input/output frequencies
Dynamically configurable via SPI/I2C interface and volatile configuration registers
The ZL30161 is a single channel Network Synchronization Clock Translator combining a single DPLL / NCO with three programmable synthesizers. The device is a fully compliant SEC (G.813) and EEC (G.8262) flexible rate conversion DPLL. It is capable of accepting and generating any frequency from 1Hz to 750MHz on up to eleven input references and up to twelve output clocks.
Click here for secure documentation
Additional Features
- Fully compliant SEC (G.813), EEC (G.8262) and Stratum 3E flexible rate conversion digital phase locked loop (DPLL)
- Programmable DPLL/Numerically Controlled Oscillators (NCO)
- Synchronizes to any clock rate from 1 Hz to 750 MHz
- Three programmable synthesizers generate any clock rate from 1 Hz to 750 MHz with maximum jitter below 0.62 ps rms
- Flexible two-stage architecture translates between arbitrary data rates, line coding rates and FEC rates
- Digital PLL filters jitter from 0.1 mHz up to 1 kHz
- Automatic hitless reference switching and digital holdover on reference fail
- Nine input references configurable as single ended or differential and two single ended input references
- Any input reference can be fed with sync (frame pulse) or clock
- Programmable DPLL can synchronize to sync pulse and sync/clock pair.
- Six LVPECL outputs and six LVCMOS outputs
- Operates from a single crystal resonator or clock oscillator
- Customer defined default device configuration available via OTP (One Time Programmable) memory, including input/output frequencies
- Dynamically configurable via SPI/I2C interface and volatile configuration registers