Microchip Technology, Inc. 2-Ch Low Cost Line Card Synchronizer ZL30146

Description
The ZL30146 OC-192/STM-64 PDH/SONET/SDH/Synchr onous Ethernet Network Interface Synchronizer is a highly integrated device that provides timing for both PDH/SONET/SDH and Ethernet network interface cards. This device is ideally suited for designs that require both a transmit timing path (backplane to PHY) and a receive timing path (PHY to backplane). Each path is controlled with separate DPLLs (Tx DPLL, Rx DPLL) which are both independently configurable through the serial interface (SPI or I2C). Click here for secure documentation Additional Features Typical Applications ITU-T G.8262 Line Cards which support 1 GbE and 10 GbE interfaces SONET/SDH line cards up to OC-192/STM-64 Features & Benefits Synchronizes to standard telecom or Ethernet backplane clocks and provides jitter filtered output clocks for SONET/SDH, PDH and Ethernet network interface cards Supports the requirements of ITU-T G.8262 for synchronous Ethernet Equipment slave Clocks Meets the SONET/SDH jitter generation requirements up to OC-192/STM-64 Two independent DPLLs provides timing for the transmit path (backplane to line rate) and the receive path (recovered line rate to backplane) Synchronizes to telecom reference clocks (2 kHz, N*8 kHz up to 77.76 MHz, 155.52 MHz) or to Ethernet reference clocks (25 MHz, 50 MHz, 62.5 MHz, 125 MHz) Selectable loop bandwidth of 14 Hz, 28 Hz, 890 Hz, 3.5 Hz, 1.7 Hz, or 0.1 Hz Supports automatic hitless reference switching and short term holdover during loss of reference inputs Generates standard SONET/SDH clock rates (e.g., 19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz, 622.08 MHz) or Ethernet clock rates (e.g., 25 MHz, 50 MHz, 125 MHz, 156.25 MHz, 312.5 MHz) for synchronizing Ethernet PHYs Programmable output synthesizer to generate telecom clock frequencies from any multiple of 8 kHz up to 100 MHz (e.g., T1/E1, DS3/E3) Generates several styles of output frame pulse with selectable pulse width, polarity, and frequency Configurable input to output delay and output to output phase alignment Configurable through a serial interface (SPI or I2C) DPLLs can be configured to provide synchronous or asynchronous clock outputs
  • 2-Ch Low Cost Line Card Synchronizer - ZL30146 - Microchip Technology, Inc.
    Microchip Technology, Inc.
Datasheet
Description
The ZL30146 OC-192/STM-64 PDH/SONET/SDH/Synchr onous Ethernet Network Interface Synchronizer is a highly integrated device that provides timing for both PDH/SONET/SDH and Ethernet network interface cards. This device is ideally suited for designs that require both a transmit timing path (backplane to PHY) and a receive timing path (PHY to backplane). Each path is controlled with separate DPLLs (Tx DPLL, Rx DPLL) which are both independently configurable through the serial interface (SPI or I2C). Click here for secure documentation Additional Features Typical Applications ITU-T G.8262 Line Cards which support 1 GbE and 10 GbE interfaces SONET/SDH line cards up to OC-192/STM-64 Features & Benefits Synchronizes to standard telecom or Ethernet backplane clocks and provides jitter filtered output clocks for SONET/SDH, PDH and Ethernet network interface cards Supports the requirements of ITU-T G.8262 for synchronous Ethernet Equipment slave Clocks Meets the SONET/SDH jitter generation requirements up to OC-192/STM-64 Two independent DPLLs provides timing for the transmit path (backplane to line rate) and the receive path (recovered line rate to backplane) Synchronizes to telecom reference clocks (2 kHz, N*8 kHz up to 77.76 MHz, 155.52 MHz) or to Ethernet reference clocks (25 MHz, 50 MHz, 62.5 MHz, 125 MHz) Selectable loop bandwidth of 14 Hz, 28 Hz, 890 Hz, 3.5 Hz, 1.7 Hz, or 0.1 Hz Supports automatic hitless reference switching and short term holdover during loss of reference inputs Generates standard SONET/SDH clock rates (e.g., 19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz, 622.08 MHz) or Ethernet clock rates (e.g., 25 MHz, 50 MHz, 125 MHz, 156.25 MHz, 312.5 MHz) for synchronizing Ethernet PHYs Programmable output synthesizer to generate telecom clock frequencies from any multiple of 8 kHz up to 100 MHz (e.g., T1/E1, DS3/E3) Generates several styles of output frame pulse with selectable pulse width, polarity, and frequency Configurable input to output delay and output to output phase alignment Configurable through a serial interface (SPI or I2C) DPLLs can be configured to provide synchronous or asynchronous clock outputs
Datasheet

Suppliers

Company
Product
Description
Supplier Links
2-Ch Low Cost Line Card Synchronizer - ZL30146 - Microchip Technology, Inc.
Microchip Technology, Inc.
Chandler, AZ, United States
2-Ch Low Cost Line Card Synchronizer
ZL30146
2-Ch Low Cost Line Card Synchronizer ZL30146
The ZL30146 OC-192/STM-64 PDH/SONET/SDH/Synchr onous Ethernet Network Interface Synchronizer is a highly integrated device that provides timing for both PDH/SONET/SDH and Ethernet network interface cards. This device is ideally suited for designs that require both a transmit timing path (backplane to PHY) and a receive timing path (PHY to backplane). Each path is controlled with separate DPLLs (Tx DPLL, Rx DPLL) which are both independently configurable through the serial interface (SPI or I2C). Click here for secure documentation Additional Features Typical Applications ITU-T G.8262 Line Cards which support 1 GbE and 10 GbE interfaces SONET/SDH line cards up to OC-192/STM-64 Features & Benefits Synchronizes to standard telecom or Ethernet backplane clocks and provides jitter filtered output clocks for SONET/SDH, PDH and Ethernet network interface cards Supports the requirements of ITU-T G.8262 for synchronous Ethernet Equipment slave Clocks Meets the SONET/SDH jitter generation requirements up to OC-192/STM-64 Two independent DPLLs provides timing for the transmit path (backplane to line rate) and the receive path (recovered line rate to backplane) Synchronizes to telecom reference clocks (2 kHz, N*8 kHz up to 77.76 MHz, 155.52 MHz) or to Ethernet reference clocks (25 MHz, 50 MHz, 62.5 MHz, 125 MHz) Selectable loop bandwidth of 14 Hz, 28 Hz, 890 Hz, 3.5 Hz, 1.7 Hz, or 0.1 Hz Supports automatic hitless reference switching and short term holdover during loss of reference inputs Generates standard SONET/SDH clock rates (e.g., 19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz, 622.08 MHz) or Ethernet clock rates (e.g., 25 MHz, 50 MHz, 125 MHz, 156.25 MHz, 312.5 MHz) for synchronizing Ethernet PHYs Programmable output synthesizer to generate telecom clock frequencies from any multiple of 8 kHz up to 100 MHz (e.g., T1/E1, DS3/E3) Generates several styles of output frame pulse with selectable pulse width, polarity, and frequency Configurable input to output delay and output to output phase alignment Configurable through a serial interface (SPI or I2C) DPLLs can be configured to provide synchronous or asynchronous clock outputs

The ZL30146 OC-192/STM-64 PDH/SONET/SDH/Synchronous Ethernet Network Interface Synchronizer is a highly integrated device that provides timing for both PDH/SONET/SDH and Ethernet network interface cards.

This device is ideally suited for designs that require both a transmit timing path (backplane to PHY) and a receive timing path (PHY to backplane). Each path is controlled with separate DPLLs (Tx DPLL, Rx DPLL) which are both independently configurable through the serial interface (SPI or I2C).

Click here for secure documentation Additional Features

  • Typical Applications
    • ITU-T G.8262 Line Cards which support 1 GbE and 10 GbE interfaces
    • SONET/SDH line cards up to OC-192/STM-64
  • Features & Benefits
    • Synchronizes to standard telecom or Ethernet backplane clocks and provides jitter filtered output clocks for SONET/SDH, PDH and Ethernet network interface cards
    • Supports the requirements of ITU-T G.8262 for synchronous Ethernet Equipment slave Clocks
    • Meets the SONET/SDH jitter generation requirements up to OC-192/STM-64
    • Two independent DPLLs provides timing for the transmit path (backplane to line rate) and the receive path (recovered line rate to backplane)
    • Synchronizes to telecom reference clocks (2 kHz, N*8 kHz up to 77.76 MHz, 155.52 MHz) or to Ethernet reference clocks (25 MHz, 50 MHz, 62.5 MHz, 125 MHz)
    • Selectable loop bandwidth of 14 Hz, 28 Hz, 890 Hz, 3.5 Hz, 1.7 Hz, or 0.1 Hz
    • Supports automatic hitless reference switching and short term holdover during loss of reference inputs
    • Generates standard SONET/SDH clock rates (e.g., 19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz, 622.08 MHz) or Ethernet clock rates (e.g., 25 MHz, 50 MHz, 125 MHz, 156.25 MHz, 312.5 MHz) for synchronizing Ethernet PHYs
    • Programmable output synthesizer to generate telecom clock frequencies from any multiple of 8 kHz up to 100 MHz (e.g., T1/E1, DS3/E3)
    • Generates several styles of output frame pulse with selectable pulse width, polarity, and frequency
    • Configurable input to output delay and output to output phase alignment
    • Configurable through a serial interface (SPI or I2C)
    • DPLLs can be configured to provide synchronous or asynchronous clock outputs
Supplier's Site Datasheet

Technical Specifications

  Microchip Technology, Inc.
Product Category Network Clock Sources
Product Number ZL30146
Product Name 2-Ch Low Cost Line Card Synchronizer
Unlock Full Specs
to access all available technical data

Related Documents

Similar Products