Silicon Labs' PCI Express clocks provide industry-leading jitter performance, compliance with PCI Express (PCIe) Gen 1/2/3 requirements, outstanding frequency flexibility and configurable AC parameters for signal integrity optimization.
The PCIe Clock family addresses the specific clock requirements of PCIe Generation 1, 2, or 3 system interfaces. This interface standard has become the industry choice as a high speed interconnect between devices and system I/Os and is used in consumer, server, storage, IP gateways, multi-function printers (MFPs) and industrial applications.
Features:
Silicon Labs’ programmable clock generator IC solutions provide any rate, any output frequency synthesis. All combinations of output frequencies can be generated exactly with 0 ppm error.
The SL28PCIe10/30/50 devices are highly integrated clock generators capable of generating PCIe compliant differential clocks, standard frequency LVCMOS system clocks and user programmable clocks. This family is based on a platform that can be factory customized to provide a mix of HCSL and LVCMOS outputs. These outputs can be programmed to produce frequencies that range from 1 to 400 MHz, with programmable AC parameters (output drive strength, rise/fall times and differential signal cross point), spread spectrum support and programmable output impedance to prevent EMI issues.
Features:
Silicon Labs' highly flexible, factory and I2C programmable and factory customizable LVCMOS clock generators can be customized to generate multiple independent non-integer-related frequencies with equivalent frequency synthesis capability of 8 PLLs, with exact frequency synthesis (0 ppm error), at significantly lower jitter, lower power and smaller size than competing solutions. Factory customized options are available to minimize EMI, including programmable edge rates, programmable impedance and programmable skew.
Silicon Labs' programmable spread spectrum clock generators feature a wide range of programming options that allow system designers to minimize electro-magnetic interference (EMI) at the application level.
Configurable parameters to reduce EMI include a wide range of signal integrity adjustments like rise/fall times, output impedance, drive strength, programmable edge rates, programmable skew and spread spectrum percentage/modulatio
Features:
Silicon Labs | Silicon Labs | Silicon Labs | |
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Product Category | IC Clocks | IC Clocks | IC Clocks |
Product Number | Si5338K | Si5338K | Si5338K |
Product Name | PCI Express (PCIe) Gen 1/2/3 Clock | Differential + LVCMOS Clock Generator | LVCMOS Clock (5+ Outputs) |
Device Type | Clock Generator | Clock Generator | Clock Generator |
Bus Interface | LVPECL; HSTL; LVDS; SSTL; LVCMOS, HCSL | LVPECL; HSTL; LVDS; SSTL; LVCMOS, HCSL | LVPECL; HSTL; LVDS; SSTL; LVCMOS, HCSL |
Package Type | QFN | QFN | QFN |
Supply Voltage | 1.8 to 3.3 volts | 1.8 to 3.3 volts | 1.8 to 3.3 volts |