Texas Instruments High-Performance Analog Clock/Timing - Clock/Timing - Clock Generators, PLLs, Frequency Synthesizers - CDC857-2DGG CDC857-2DGG

The CDC857-2DGG is a phase-lock loop (PLL) clock driver designed for high-performance clock distribution in Double Data Rate Synchronous DRAM applications. It distributes one differential clock input to ten differential outputs, providing low-skew and low-jitter copies of the input clock signal. The device operates at a supply voltage of 2.5 V for both the PLL and output buffers, and features an external feedback mechanism to synchronize outputs with the clock input. This clock driver includes an integrated loop filter, eliminating the need for external RC networks, which simplifies design and reduces component count. The outputs can be enabled or disabled via a single control input, allowing for flexible operation. The CDC857-2DGG is packaged in a 48-pin Thin Shrink Small-Outline Package (TSSOP) and is characterized for operation within a temperature range of 0¬8C to 85¬8C. Additionally, it supports spread spectrum clocking to help reduce electromagnetic interference (EMI).