Semiconductor fabrication, traditionally including Front-End-Of-The-Lin
e (FEOL), Middle-Of-The-Line, (MOL), and Back-End-Of-The-Line (BEOL), constitutes the entire process flow for manufacturing modern computer chips. The typical FEOL processes include wafer preparation, isolation, well formation, gate patterning, spacer, extension and source/drain implantation, silicide formation, and dual stress liner formation. The MOL is mainly gate contact (CA) formation, which is an increasingly challenging part of the whole fabrication flow, particularly for lithography patterning. The state-of-the-art semiconductor chips, the so called 14 nm node of Complementary MetalâOxideâSemi
conductor (CMOS) chips, in mass production features a second generation three dimensional (3D) FinFET, a metal one pitch of about 55 nm and copper (Cu)/low-k (and air-gap) interconnects. The Cu/low-k interconnects are fabricated predominantly with a dual damascene process using plasma-enhanced CVD (PECVD) deposited interlayer dielectric (ILDs), PVD Cu barrier and electrochemically plated Cu wire materials. Successful fabrication and qualification of modern semiconductor chip products requires a deep understanding of the intricate interplay between the materials and the processes employed. This course provides an overview of modern semiconductor fabrication flow, its integration schemes, fabrication processes and key factors affecting yields. It highlights unique challenges in lithography for FEOL, MOL and BEOL and discusses potential solutions as well as practical techniques. The goal of this course is to provide materials, process and integration engineers a fundamental basis to develop materials and processes for FEOL, MOL and BEOL patterning and to trouble shoot fabrication problems. This course will also introduce new materials (such as high-K/metal gate or HKMG, III-V materials), new device and interconnect structures (such as FinFET/ Trigate, nanowires, Cu/air-gap interconnects) and new integrations (such as 3D IC, Through-Silicon Via or TSV) as well as recent lithography innovations (such as double patterning and directed self-assembly, DSA).
Semiconductor fabrication, traditionally including Front-End-Of-The-Line (FEOL), Middle-Of-The-Line, (MOL), and Back-End-Of-The-Line (BEOL), constitutes the entire process flow for manufacturing modern computer chips. The typical FEOL processes include wafer preparation, isolation, well formation, gate patterning, spacer, extension and source/drain implantation, silicide formation, and dual stress liner formation. The MOL is mainly gate contact (CA) formation, which is an increasingly challenging part of the whole fabrication flow, particularly for lithography patterning. The state-of-the-art semiconductor chips, the so called 14 nm node of Complementary Metal–Oxide–Semiconductor (CMOS) chips, in mass production features a second generation three dimensional (3D) FinFET, a metal one pitch of about 55 nm and copper (Cu)/low-k (and air-gap) interconnects. The Cu/low-k interconnects are fabricated predominantly with a dual damascene process using plasma-enhanced CVD (PECVD) deposited interlayer dielectric (ILDs), PVD Cu barrier and electrochemically plated Cu wire materials. Successful fabrication and qualification of modern semiconductor chip products requires a deep understanding of the intricate interplay between the materials and the processes employed. This course provides an overview of modern semiconductor fabrication flow, its integration schemes, fabrication processes and key factors affecting yields. It highlights unique challenges in lithography for FEOL, MOL and BEOL and discusses potential solutions as well as practical techniques. The goal of this course is to provide materials, process and integration engineers a fundamental basis to develop materials and processes for FEOL, MOL and BEOL patterning and to trouble shoot fabrication problems. This course will also introduce new materials (such as high-K/metal gate or HKMG, III-V materials), new device and interconnect structures (such as FinFET/ Trigate, nanowires, Cu/air-gap interconnects) and new integrations (such as 3D IC, Through-Silicon Via or TSV) as well as recent lithography innovations (such as double patterning and directed self-assembly, DSA).
