SPIE - Education Principles and Practical Implementation of Multiple Patterning SC885

This course provides attendees with a basic working knowledge of the fundamentals and implementation principles of what industry calls with a generic name "double patterning” but in reality it is a multi-patterning technology. This course will tackle the interdisciplinary characteristics of the multipatterning processes examining several pitch division techniques, from double to triple, quadruple or even more split steps, with focus on the key technology components, such as, but not limited to, (a) resolution and lithography options, (b) layout, ground rules and split compliance, (c) process and material, that are combined to create an electrically functional device layer from multiple patterning steps. We will discuss single to multiple patterning pitch-split practical implementations adding complementary and combinatorial techniques based on pitch-divided gratings connected with a cut and/or a block masking layer. The course presents the lithographic and patterning alternatives of various pitch-split techniques, for example, LithoEtch, LEn where n≥2 and multiple SelfAligned spacer film depositions, like SADP and SAQP. It will underline the interactions between layout style, split compliance, layer polarity, feature bias defined by split process characteristics and will draw attention to the constraints to integrate the pitch-split patterning steps into a complete CMOS process flow. In addition, the course provides information on the materials and material combinations used in multiple patterning processes illustrated by recent industry developments to increase the structural robustness of pitch divided high aspect ratio features and the anti-spacer / cut mask-less approach. Special attention is given to the unique characteristics of multiple patterning metrology and process control, in particular to model overlay effects into comprehensive CDU budgets supporting the tight process tolerances of the scaling nodes. The course examines the CDU and overlay budget contributors and defines basic requirements for metrology tools performances to support multipatterning. We will illustrate multipatterning utilization on today’s 3D transistors architecture, FinFet and Nanowires, applied on FEOL and BEOL layers, with unidirectional gratings and cuts or blocks that are needed to create the 2D layout intent. The course offers comprehensive analysis of the combinatorial multiple patterning flows, LE^n, SADP, SAQP with associated cut or block masking layers based on the new Edge Placement Error, EPE, metric, assessing pattern quality for manufacturability. Practical and useful examples from critical device layers of memory and logic devices are included throughout, with particular consideration on how multiple splits operate on device sequential layers using computational lithography optimized splits. The course includes extensive references of relevant publications on double/ multiple patterning processes.