SPIE - Education Design Technology Co-Optimization in the Era of Sub-resolution IC Scaling SC1155

Design Technology CoOptimization (DTCO) is a mediation process that aims to ensure competitive technology architecture definition while avoiding schedule or yield risks caused by unrealistically aggressive process assumptions. DTCO has evolved from lithography friendly design (LfD) and design for manufacturability (DfM) but differs from these approaches in that the goal is not just to communicate process driven constraints to the designers but to negotiate a more optimal tradeoff between designers’ needs and process developers’ concerns. To achieve a sense of shared ownership and enable innovative solutions, it is important for the process developers to understand the high level goals of the design community. To that end, this short course reviews the fundamental system-on-chip (SoC) design objectives as well as the resulting topological constraints on different building blocks of a SoC, such as standard cells, embedded memories, analog components and place and route flows. The DTCO process is explained as a series of steps that incrementally refine the technology architecture using concepts such as: design driven rules definition, design rule arc analysis, and construct based technology definition. The efficacy of DTCO is illustrated using detailed case-studies at N14 and beyond. As an example of how the communicated material might be applied, the course presents a cautious and very preliminary look at the specific design challenges of scaling to the 7NM node using multiple exposure 193i patterning. It concludes with how holistic DTCO at N7 and beyond is essential to driving profitable scaling by considering process, device, interconnect, circuit and architecture considerations. While it is impossible to present a simple ‘how to’ manual for DTCO, the goal of this course is to break down the abstract concept of DTCO into specific actionable components that collectively play an increasing role in maintaining the industries aggressive pace of semiconductor scaling.