The SiT95211 offers programmable quad fractional frequency generation and translation with flexible input to output frequency translation options. Ultra high jitter performance DPLL supports up to 4 differential or single-ended input clocks that are common for all the 4 fractional PLLs and provides 12 differential output clocks. The clock outputs can be derived from any of the 4 PLLs in a fully flexible manner. This device is fully programmable with the I2C/SPI interface or an on-chip one-time programmable non-volatile memory for factory pre-programmed devices.
Lower phase noise minimizes bit error rate and increases design margin in 56G/112G PAM4 I/O systems
Better signal integrity increases design margin and leads to faster time to market
Higher clock tree integration reduces system BOM and increases overall reliability
The SiT95211 offers programmable quad fractional frequency generation and translation with flexible input to output frequency translation options. Ultra high jitter performance DPLL supports up to 4 differential or single-ended input clocks that are common for all the 4 fractional PLLs and provides 12 differential output clocks. The clock outputs can be derived from any of the 4 PLLs in a fully flexible manner. This device is fully programmable with the I2C/SPI interface or an on-chip one-time programmable non-volatile memory for factory pre-programmed devices.
- Lower phase noise minimizes bit error rate and increases design margin in 56G/112G PAM4 I/O systems
- Better signal integrity increases design margin and leads to faster time to market
- Higher clock tree integration reduces system BOM and increases overall reliability
