The 14-bit ISL5314 provides a complete Direct Digital Synthesizer (DDS) system in a single 48 Ld LQFP package. A 48-bit Programmable Carrier NCO (numerically controlled oscillator) and a high speed 14-bit DAC (digital-to-analog converter) are integrated into a stand alone DDS.brbr The DDS accepts 48-bit center and offset frequency control information via a parallel processor interface. A 40-bit frequency tuning word can also be loaded via an asynchronous serial interface. Modulation control is provided by 3 external pins. The PH0 and PH1 pins select phase offsets of 0°, 90°, 180° and 270°, while the ENOFR pin enables or zeros the offset frequency word to the phase accumulator.brbr The parallel processor interface has an 8-bit write-only data input C(7:0), a 4-bit address A(3:0) bus, a Write Strobe (WR), and a Write Enable (span style="text-decorati
on: /spanThe processor can update all registers simultaneously by loading a set of master registers, then transfer all master registers to the slave registers by asserting the span style="text-decorati
on: overline"UPDATE/span pin.
The 14-bit ISL5314 provides a complete Direct Digital Synthesizer (DDS) system in a single 48 Ld LQFP package. A 48-bit Programmable Carrier NCO (numerically controlled oscillator) and a high speed 14-bit DAC (digital-to-analog converter) are integrated into a stand alone DDS.brbr The DDS accepts 48-bit center and offset frequency control information via a parallel processor interface. A 40-bit frequency tuning word can also be loaded via an asynchronous serial interface. Modulation control is provided by 3 external pins. The PH0 and PH1 pins select phase offsets of 0°, 90°, 180° and 270°, while the ENOFR pin enables or zeros the offset frequency word to the phase accumulator.brbr The parallel processor interface has an 8-bit write-only data input C(7:0), a 4-bit address A(3:0) bus, a Write Strobe (WR), and a Write Enable (span style="text-decoration: /spanThe processor can update all registers simultaneously by loading a set of master registers, then transfer all master registers to the slave registers by asserting the span style="text-decoration: overline"UPDATE/span pin.
