The 95V850AGLF from Quarktwin Technology Ltd. is a DDR Phase Lock Loop (PLL) clock driver designed for applications requiring precise timing. It operates within a frequency range of 60 MHz to 210 MHz, making it suitable for high-speed memory interfaces. The device features low skew and low jitter characteristics, with cycle-to-cycle jitter specified at less than 60 ps and output-to-output skew also under 60 ps. This clock driver supports various input standards, including LVTTL, LVPECL, LVDS, and LVCMOS, with a switching amplitude of 400 mV. It includes feedback pins for synchronization and is tolerant to spread spectrum inputs. The device can operate in a bypass mode and is packaged in a compact 48-pin TSSOP format, which measures 6.10 mm in body size with a 0.5 mm pitch. Engineers looking for a reliable clock driver for DDR applications may find the 95V850AGLF a suitable choice due to its robust performance specifications and versatile input compatibility.
Memory, DDR Clock Buffer/Driver, Multiplexer IC 210MHz 1 Output 48-TSSOP
IC CLK BUF DDR 210MHZ 1CIRC
| Quarktwin Technology Ltd. | Lingto Electronic Limited | |
|---|---|---|
| Product Category | IC Clocks | IC Clocks |
| Product Number | 95V850AGLF | 95V850AGLF |
| Product Name | Application Specific Clock/Timing | Clock/Timing - Application Specific |
| Device Type | Clock Driver | Clock Generator |
| Bus Interface | SSTL-2 | |
| Package Type | Surface Mount; 48-TFSOP (0.240\", 6.10mm Width) | Surface Mount; Surface Mount |
| Supply Voltage | 2.3 to 2.7 volts |
