The 74LVT162374 is a high performance BiCMOS product designed for VCC operation at 3.3 V.
The 74LVT162374 is designed with 30 Ω series resistance in both the HIGH and LOW states of the output. This design reduces line noise in applications such as memory address drivers, clock drivers, and bus receivers/transmitte
rs.
This device is a 16-bit edge-triggered D-type flip-flop featuring non-inverting 3-state outputs. The device can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CP), the Q outputs of the flip-flop take on the logic levels set up at the D inputs.
Features and benefits 16-bit edge-triggered flip-flop 3-state buffers Output capability: +12 mA and −12 mA TTL input and output switching levels Input and output interface capability to systems at 5 V supply Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs Live insertion and extraction permitted Outputs include series resistance of 30 Ω making external resistors unnecessary Power-up reset Power-up 3-state No bus current loading when output is tied to 5 V bus Latch-up protection: JESD78B Class II exceeds 500 mA ESD protection: HBM: JESD22-A114F exceeds 2000 V MM: JESD22-A115-A exceeds 200 V
The 74LVT162374 is a high performance BiCMOS product designed for VCC operation at 3.3 V.
The 74LVT162374 is designed with 30 Ω series resistance in both the HIGH and LOW states of the output. This design reduces line noise in applications such as memory address drivers, clock drivers, and bus receivers/transmitters.
This device is a 16-bit edge-triggered D-type flip-flop featuring non-inverting 3-state outputs. The device can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CP), the Q outputs of the flip-flop take on the logic levels set up at the D inputs.
Features and benefits
- 16-bit edge-triggered flip-flop
- 3-state buffers
- Output capability: +12 mA and −12 mA
- TTL input and output switching levels
- Input and output interface capability to systems at 5 V supply
- Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs
- Live insertion and extraction permitted
- Outputs include series resistance of 30 Ω making external resistors unnecessary
- Power-up reset
- Power-up 3-state
- No bus current loading when output is tied to 5 V bus
- Latch-up protection:
- JESD78B Class II exceeds 500 mA
- ESD protection:
- HBM: JESD22-A114F exceeds 2000 V
- MM: JESD22-A115-A exceeds 200 V
