Nexperia B.V. 16-bit edge-triggered D-type flip-flop with 30 Ohm series termination resistors; 5 V input/output tolerant; 3-state 74LVCH162374ADGG:1

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16-bit edge-triggered D-type flip-flop with 30 Ohm series termination resistors; 5 V input/output tolerant; 3-state - 74LVCH162374ADGG:1 - Nexperia B.V.
Nijmegen, Netherlands
16-bit edge-triggered D-type flip-flop with 30 Ohm series termination resistors; 5 V input/output tolerant; 3-state
74LVCH162374ADGG:1
16-bit edge-triggered D-type flip-flop with 30 Ohm series termination resistors; 5 V input/output tolerant; 3-state 74LVCH162374ADGG:1
The 74LVCH162374A is a 16-bit edge triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications. The device consists of two sections of 8 edge-triggered flip-flops. A clock (CP) input and an output enable (OE) are provided for each octal. Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these devices in mixed 3.3 V and 5 V applications. The flip-flops store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW to HIGH CP transition. When OE is LOW, the contents of the flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. Bus hold on data inputs eliminates the need for external pull-up resistors to hold unused inputs. To reduce line noise, 30 Ω series termination resistors are included in both high and low output stages. Features and benefits 5 V tolerant inputs/outputs for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V CMOS low power consumption Multibyte flow-through standard pinout architecture Multiple low inductance supply pins for minimum noise and ground bounce Direct interface with TTL levels All data inputs have bus hold High-impedance outputs when VCC = 0 V Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-B exceeds 200 V CDM JESD22-C101E exceeds 1000 V Specified from -40 °C to +85 °C and -40 °C to +125 °C

The 74LVCH162374A is a 16-bit edge triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications. The device consists of two sections of 8 edge-triggered flip-flops. A clock (CP) input and an output enable (OE) are provided for each octal. Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these devices in mixed 3.3 V and 5 V applications. The flip-flops store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW to HIGH CP transition. When OE is LOW, the contents of the flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops.

Bus hold on data inputs eliminates the need for external pull-up resistors to hold unused inputs.

To reduce line noise, 30 Ω series termination resistors are included in both high and low output stages.

Features and benefits

  • 5 V tolerant inputs/outputs for interfacing with 5 V logic
  • Wide supply voltage range from 1.2 V to 3.6 V
  • CMOS low power consumption
  • Multibyte flow-through standard pinout architecture
  • Multiple low inductance supply pins for minimum noise and ground bounce
  • Direct interface with TTL levels
  • All data inputs have bus hold
  • High-impedance outputs when VCC = 0 V
  • Complies with JEDEC standard:
    • JESD8-7A (1.65 V to 1.95 V)
    • JESD8-5A (2.3 V to 2.7 V)
    • JESD8-C/JESD36 (2.7 V to 3.6 V)
  • ESD protection:
    • HBM JESD22-A114F exceeds 2000 V
    • MM JESD22-A115-B exceeds 200 V
    • CDM JESD22-C101E exceeds 1000 V
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C
Supplier's Site Datasheet
 - 74LVCH162374ADGG:1 - Rochester Electronics
Newburyport, MA, United States
Nexperia 74LVCH162374A - 16-bit edge-triggered D-type flip-flop

Nexperia 74LVCH162374A - 16-bit edge-triggered D-type flip-flop

Supplier's Site Datasheet
Logic - Flip Flops - 74LVCH162374ADGG:1 - Lingto Electronic Limited
Shenzhen, China
Logic - Flip Flops
74LVCH162374ADGG:1
Logic - Flip Flops 74LVCH162374ADGG:1
IC FF D-TYPE DUAL 8BIT 48TSSOP

IC FF D-TYPE DUAL 8BIT 48TSSOP

Supplier's Site Datasheet
Flip Flops - 1727-74LVCH162374ADGG:1TR-ND - DigiKey
Thief River Falls, MN, United States
IC FF D-TYPE DUAL 8BIT 48TSSOP

IC FF D-TYPE DUAL 8BIT 48TSSOP

Supplier's Site Datasheet
Flip Flops - 1727-74LVCH162374ADGG:1DKR-ND - DigiKey
Thief River Falls, MN, United States
IC FF D-TYPE DUAL 8BIT 48TSSOP

IC FF D-TYPE DUAL 8BIT 48TSSOP

Supplier's Site Datasheet
Flip Flops - 1727-74LVCH162374ADGG:1CT-ND - DigiKey
Thief River Falls, MN, United States
IC FF D-TYPE DUAL 8BIT 48TSSOP

IC FF D-TYPE DUAL 8BIT 48TSSOP

Supplier's Site Datasheet

Technical Specifications

  Nexperia B.V. Rochester Electronics Lingto Electronic Limited DigiKey
Product Category Flip-Flops Flip-Flops Flip-Flops Flip-Flops
Product Number 74LVCH162374ADGG:1 74LVCH162374ADGG:1 74LVCH162374ADGG:1 1727-74LVCH162374ADGG:1TR-ND
Product Name 16-bit edge-triggered D-type flip-flop with 30 Ohm series termination resistors; 5 V input/output tolerant; 3-state Logic - Flip Flops Flip Flops
Flip-Flop Type D D
Supply Voltage 1.2V; 1.5V; 1.8V; 2.5V; 3V; 3.3V; 3.6V; 1.2 - 3.6 1.65V ~ 3.6V
Output Characteristics 3-State 3-State
Features ESD Protection
Propagation Delay 3.8 ns 6.8 ns
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