Nexperia B.V. Single D-type flip-flop with set and reset; positive edge trigger 74LVC2G74GN,115

The 74LVC2G74 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using I_OFF. The I_OFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Features and benefits

• Wide supply voltage range from 1.65 V to 5.5 V
• Overvoltage tolerant inputs to 5.5 V
• High noise immunity
• Complies with JEDEC standard:
• JESD8-7 (1.65 V to 1.95 V)
• JESD8-5 (2.3 V to 2.7 V)
• JESD8-B/JESD36 (2.7 V to 3.6 V)
• ±24 mA output drive (V_CC = 3.0 V)
• ESD protection:
• HBM JESD22-A114F exceeds 2000 V
• MM JESD22-A115-A exceeds 200 V
• CMOS low power consumption
• Latch-up performance exceeds 250 mA
• Direct interface with TTL levels
• I_OFF circuitry provides partial Power-down mode operation
• Multiple package options
• Specified from -40 °C to +85 °C and -40 °C to +125 °C

IC FF D-TYPE SNGL 1BIT 8XSON

IC FF D-TYPE SNGL 1BIT 8XSON

IC FF D-TYPE SNGL 1BIT 8XSON

IC FF D-TYPE SNGL 1BIT 8XSON

74LVC2G74 - Single D-type flip-flop with set and reset; positive edge trigger