Nexperia B.V. Single D-type flip-flop; positive-edge trigger 74LVC1G80GW,125

Description
The 74LVC1G80 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and its complement will appear at the Q output. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. Features and benefits Wide supply voltage range from 1.65 V to 5.5 V Overvoltage tolerant inputs to 5.5 V High noise immunity ±24 mA output drive (VCC = 3.0 V) CMOS low power dissipation Direct interface with TTL levels IOFF circuitry provides partial Power-down mode operation Latch-up performance exceeds 250 mA Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8C (2.7 V to 3.6 V) JESD36 (4.5 V to 5.5 V) ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Multiple package options Specified from -40 °C to +85 °C and -40 °C to +125 °C.
  • Single D-type flip-flop; positive-edge trigger - 74LVC1G80GW,125 - Nexperia B.V.
    Nexperia B.V.
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  • Flip Flops - 1727-6081-1-ND - DigiKey
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  • Integrated Circuits (ICs) - Logic - Flip Flops - 74LVC1G80GW,125 - Shenzhen Shengyu Electronics Technology Limited
    Shenzhen Shengyu Electronics Technology Limited
  • Flip Flops - 74LVC1G80GW,125 - Quarktwin Technology Ltd.
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  • 74LVC1G80GW,125 - Rochester Electronics
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  • Logic - Flip Flops - 74LVC1G80GW,125 - Lingto Electronic Limited
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  • Flip-Flop, D-Type, 200Mhz, Tssop-5; Logic Family / Base Number Nexperia - 93X4947 - Newark, An Avnet Company
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Request a Quote Datasheet
Description
The 74LVC1G80 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and its complement will appear at the Q output. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. Features and benefits Wide supply voltage range from 1.65 V to 5.5 V Overvoltage tolerant inputs to 5.5 V High noise immunity ±24 mA output drive (VCC = 3.0 V) CMOS low power dissipation Direct interface with TTL levels IOFF circuitry provides partial Power-down mode operation Latch-up performance exceeds 250 mA Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8C (2.7 V to 3.6 V) JESD36 (4.5 V to 5.5 V) ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Multiple package options Specified from -40 °C to +85 °C and -40 °C to +125 °C.
Request a Quote Datasheet

Suppliers

Company
Product
Description
Supplier Links
Single D-type flip-flop; positive-edge trigger - 74LVC1G80GW,125 - Nexperia B.V.
Nexperia B.V.
Nijmegen, Netherlands
Single D-type flip-flop; positive-edge trigger
74LVC1G80GW,125
Single D-type flip-flop; positive-edge trigger 74LVC1G80GW,125
The 74LVC1G80 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and its complement will appear at the Q output. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. Features and benefits Wide supply voltage range from 1.65 V to 5.5 V Overvoltage tolerant inputs to 5.5 V High noise immunity ±24 mA output drive (VCC = 3.0 V) CMOS low power dissipation Direct interface with TTL levels IOFF circuitry provides partial Power-down mode operation Latch-up performance exceeds 250 mA Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8C (2.7 V to 3.6 V) JESD36 (4.5 V to 5.5 V) ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Multiple package options Specified from -40 °C to +85 °C and -40 °C to +125 °C.

The 74LVC1G80 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and its complement will appear at the Q output. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Features and benefits

  • Wide supply voltage range from 1.65 V to 5.5 V
  • Overvoltage tolerant inputs to 5.5 V
  • High noise immunity
  • ±24 mA output drive (VCC = 3.0 V)
  • CMOS low power dissipation
  • Direct interface with TTL levels
  • IOFF circuitry provides partial Power-down mode operation
  • Latch-up performance exceeds 250 mA
  • Complies with JEDEC standard:
    • JESD8-7 (1.65 V to 1.95 V)
    • JESD8-5 (2.3 V to 2.7 V)
    • JESD8C (2.7 V to 3.6 V)
    • JESD36 (4.5 V to 5.5 V)
  • ESD protection:
    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
  • Multiple package options
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C.
Supplier's Site Datasheet
Flip Flops - 1727-6081-6-ND - DigiKey
DigiKey
Thief River Falls, MN, United States
Flip Flops
1727-6081-6-ND
Flip Flops 1727-6081-6-ND
Flip Flop 1 Element D-Type 1 Bit Positive Edge 5-TSSOP, SC-70-5, SOT-353

Flip Flop 1 Element D-Type 1 Bit Positive Edge 5-TSSOP, SC-70-5, SOT-353

Buy Now Datasheet
Flip Flops - 1727-6081-2-ND - DigiKey
DigiKey
Thief River Falls, MN, United States
Flip Flops
1727-6081-2-ND
Flip Flops 1727-6081-2-ND
Flip Flop 1 Element D-Type 1 Bit Positive Edge 5-TSSOP, SC-70-5, SOT-353

Flip Flop 1 Element D-Type 1 Bit Positive Edge 5-TSSOP, SC-70-5, SOT-353

Buy Now Datasheet
Flip Flops - 1727-6081-1-ND - DigiKey
DigiKey
Thief River Falls, MN, United States
Flip Flops
1727-6081-1-ND
Flip Flops 1727-6081-1-ND
Flip Flop 1 Element D-Type 1 Bit Positive Edge 5-TSSOP, SC-70-5, SOT-353

Flip Flop 1 Element D-Type 1 Bit Positive Edge 5-TSSOP, SC-70-5, SOT-353

Buy Now Datasheet
Integrated Circuits (ICs) - Logic - Flip Flops - 74LVC1G80GW,125 - Shenzhen Shengyu Electronics Technology Limited
Shenzhen Shengyu Electronics Technology Limited
Futian, China
Integrated Circuits (ICs) - Logic - Flip Flops
74LVC1G80GW,125
Integrated Circuits (ICs) - Logic - Flip Flops 74LVC1G80GW,125
IC FF D-TYPE SNGL 1BIT 5TSSOP

IC FF D-TYPE SNGL 1BIT 5TSSOP

Supplier's Site
Flip Flops - 74LVC1G80GW,125 - Quarktwin Technology Ltd.
Quarktwin Technology Ltd.
Shenzhen, Guangdong, China
Flip Flops
74LVC1G80GW,125
Flip Flops 74LVC1G80GW,125
Flip Flop 1 Element D-Type 1 Bit Positive Edge 5-TSSOP, SC-70-5, SOT-353

Flip Flop 1 Element D-Type 1 Bit Positive Edge 5-TSSOP, SC-70-5, SOT-353

Buy Now Datasheet
- 74LVC1G80GW,125 - Rochester Electronics
Rochester Electronics
Newburyport, MA, United States
74LVC1G80GW,125
74LVC1G80GW,125
D Flip-Flop, LVC/LCX/Z Series, 1-Func, Positive Edge Triggered, 1-Bit, Inverted Output, CMOS, PDSO5

D Flip-Flop, LVC/LCX/Z Series, 1-Func, Positive Edge Triggered, 1-Bit, Inverted Output, CMOS, PDSO5

Supplier's Site Datasheet
Logic - Flip Flops - 74LVC1G80GW,125 - Lingto Electronic Limited
Lingto Electronic Limited
Shenzhen, China
Logic - Flip Flops
74LVC1G80GW,125
Logic - Flip Flops 74LVC1G80GW,125
IC FF D-TYPE SNGL 1BIT 5TSSOP

IC FF D-TYPE SNGL 1BIT 5TSSOP

Supplier's Site Datasheet
Flip-Flop, D-Type, 200Mhz, Tssop-5; Logic Family / Base Number Nexperia - 93X4947 - Newark, An Avnet Company
Newark, An Avnet Company
Chicago, IL, United States
Flip-Flop, D-Type, 200Mhz, Tssop-5; Logic Family / Base Number Nexperia
93X4947
Flip-Flop, D-Type, 200Mhz, Tssop-5; Logic Family / Base Number Nexperia 93X4947
FLIP-FLOP, D-TYPE, 200MHZ, TSSOP-5; Logic Family / Base Number:74LVC1G80; Flip-Flop Type:D; Propagation Delay:-; Frequency:200MHz; Output Current:50mA; Logic Case Style:TSSOP; No. of Pins:5Pins; Trigger Type:Positive Edge; IC Output RoHS Compliant: Yes

FLIP-FLOP, D-TYPE, 200MHZ, TSSOP-5; Logic Family / Base Number:74LVC1G80; Flip-Flop Type:D; Propagation Delay:-; Frequency:200MHz; Output Current:50mA; Logic Case Style:TSSOP; No. of Pins:5Pins; Trigger Type:Positive Edge; IC Output RoHS Compliant: Yes

Supplier's Site Datasheet

Technical Specifications

  Nexperia B.V. DigiKey Shenzhen Shengyu Electronics Technology Limited Quarktwin Technology Ltd. Rochester Electronics Lingto Electronic Limited Newark, An Avnet Company
Product Category Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops
Product Number 74LVC1G80GW,125 1727-6081-6-ND 74LVC1G80GW,125 74LVC1G80GW,125 74LVC1G80GW,125 74LVC1G80GW,125 93X4947
Product Name Single D-type flip-flop; positive-edge trigger Flip Flops Integrated Circuits (ICs) - Logic - Flip Flops Flip Flops Logic - Flip Flops Flip-Flop, D-Type, 200Mhz, Tssop-5; Logic Family / Base Number Nexperia
Flip-Flop Type D D D
Triggering Positive-edge Triggered Positive-edge Triggered Positive-edge Triggered
Supply Voltage 1.8V; 2.5V; 3V; 3.3V; 3.6V; 5V; 1.65 - 5.5 1.65V ~ 5.5V 1.65V ~ 5.5V
Features ESD Protection
Propagation Delay 2.4 ns 4.5 ns
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