The 74AUP3G17 provides three Schmitt trigger buffers. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.
This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
The inputs switch at different points for positive and negative-going signals. The difference between the positive voltage VT+ and the negative voltage VT- is defined as the input hysteresis voltage VH.
Features and benefits
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Low static power consumption; ICC = 0.9 μA (maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of VCC
IOFF circuitry provides partial Power-down mode operation
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Multiple package options
Specified from -40 °C to +85 °C and -40 °C to +125 °C
The 74AUP3G17 provides three Schmitt trigger buffers. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.
This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
The inputs switch at different points for positive and negative-going signals. The difference between the positive voltage VT+ and the negative voltage VT- is defined as the input hysteresis voltage VH.
Features and benefits
- Wide supply voltage range from 0.8 V to 3.6 V
- High noise immunity
- Low static power consumption; ICC = 0.9 μA (maximum)
- Latch-up performance exceeds 100 mA per JESD 78 Class II
- Inputs accept voltages up to 3.6 V
- Low noise overshoot and undershoot < 10 % of VCC
- IOFF circuitry provides partial Power-down mode operation
- ESD protection:
- HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V
- CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
- Multiple package options
- Specified from -40 °C to +85 °C and -40 °C to +125 °C
