Nexperia B.V. Low-power dual 2-input NAND gate; open drain 74AUP2G38GN,115

Description
The 74AUP2G38 provides the dual 2-input NAND gate with open-drain output. The output of the device is an open drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down. Features and benefits Wide supply voltage range from 0.8 V to 3.6 V High noise immunity Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-B (2.7 V to 3.6 V) Low static power consumption; ICC = 0.9 μA (maximum) Latch-up performance exceeds 100 mA per JESD78B Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of VCC IOFF circuitry provides partial Power-down mode operation ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Multiple package options Specified from -40 °C to +85 °C and -40 °C to +125 °C
Request a Quote Datasheet
Description
The 74AUP2G38 provides the dual 2-input NAND gate with open-drain output. The output of the device is an open drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down. Features and benefits Wide supply voltage range from 0.8 V to 3.6 V High noise immunity Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-B (2.7 V to 3.6 V) Low static power consumption; ICC = 0.9 μA (maximum) Latch-up performance exceeds 100 mA per JESD78B Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of VCC IOFF circuitry provides partial Power-down mode operation ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Multiple package options Specified from -40 °C to +85 °C and -40 °C to +125 °C
Request a Quote Datasheet

Suppliers

Company
Product
Description
Supplier Links
Low-power dual 2-input NAND gate; open drain - 74AUP2G38GN,115 - Nexperia B.V.
Nijmegen, Netherlands
Low-power dual 2-input NAND gate; open drain
74AUP2G38GN,115
Low-power dual 2-input NAND gate; open drain 74AUP2G38GN,115
The 74AUP2G38 provides the dual 2-input NAND gate with open-drain output. The output of the device is an open drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down. Features and benefits Wide supply voltage range from 0.8 V to 3.6 V High noise immunity Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-B (2.7 V to 3.6 V) Low static power consumption; ICC = 0.9 μA (maximum) Latch-up performance exceeds 100 mA per JESD78B Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of VCC IOFF circuitry provides partial Power-down mode operation ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Multiple package options Specified from -40 °C to +85 °C and -40 °C to +125 °C

The 74AUP2G38 provides the dual 2-input NAND gate with open-drain output. The output of the device is an open drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.

Features and benefits

  • Wide supply voltage range from 0.8 V to 3.6 V
  • High noise immunity
  • Complies with JEDEC standards:
    • JESD8-12 (0.8 V to 1.3 V)
    • JESD8-11 (0.9 V to 1.65 V)
    • JESD8-7 (1.2 V to 1.95 V)
    • JESD8-5 (1.8 V to 2.7 V)
    • JESD8-B (2.7 V to 3.6 V)
  • Low static power consumption; ICC = 0.9 μA (maximum)
  • Latch-up performance exceeds 100 mA per JESD78B Class II
  • Inputs accept voltages up to 3.6 V
  • Low noise overshoot and undershoot < 10 % of VCC
  • IOFF circuitry provides partial Power-down mode operation
  • ESD protection:
    • HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V
    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
  • Multiple package options
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C
Supplier's Site Datasheet
Dual Logic IC 705-74AUP2G38GN,115
IC GATE NAND 2CH 2-INP 8XSON Product overview: 74AUP2G38GN,115 from Nexperia is a Logic IC for digital control, signal routing, level logic, timing, buffering, and embedded board design. It is useful for engineers and buyers comparing datasheets, replacement parts, BOM lines, package options, lifecycle status, and procurement availability. Key searchable attributes include Dual. Search-friendly keywords include logic IC, gate, inverter, buffer, digital signal, Dual, Gates and Inverters. This listing supports clearer product discovery for industrial, commercial, repair, automation, power, sensing, and embedded system projects. Product number 705-74AUP2G38GN,115 can be used for catalog matching and distributor lookup.

IC GATE NAND 2CH 2-INP 8XSON Product overview: 74AUP2G38GN,115 from Nexperia is a Logic IC for digital control, signal routing, level logic, timing, buffering, and embedded board design. It is useful for engineers and buyers comparing datasheets, replacement parts, BOM lines, package options, lifecycle status, and procurement availability. Key searchable attributes include Dual. Search-friendly keywords include logic IC, gate, inverter, buffer, digital signal, Dual, Gates and Inverters. This listing supports clearer product discovery for industrial, commercial, repair, automation, power, sensing, and embedded system projects. Product number 705-74AUP2G38GN,115 can be used for catalog matching and distributor lookup.

Supplier's Site Datasheet
Gates and Inverters - 1727-74AUP2G38GN,115TR-ND - DigiKey
Thief River Falls, MN, United States
Gates and Inverters
1727-74AUP2G38GN,115TR-ND
Gates and Inverters 1727-74AUP2G38GN,115TR-ND
NAND Gate IC 2 Channel Open Drain 8-XSON (1.2x1)

NAND Gate IC 2 Channel Open Drain 8-XSON (1.2x1)

Buy Now Datasheet
 - 74AUP2G38GN,115 - Rochester Electronics
Newburyport, MA, United States
NAND Gate, AUP/ULP/V Series, 2-Func, CMOS, PDSO8

NAND Gate, AUP/ULP/V Series, 2-Func, CMOS, PDSO8

Supplier's Site Datasheet
Logic - Gates and Inverters - 74AUP2G38GN,115 - Lingto Electronic Limited
Shenzhen, China
Logic - Gates and Inverters
74AUP2G38GN,115
Logic - Gates and Inverters 74AUP2G38GN,115
IC GATE NAND OD 2CH 2-INP 8XSON

IC GATE NAND OD 2CH 2-INP 8XSON

Supplier's Site Datasheet
Gates and Inverters - 74AUP2G38GN,115 - Quarktwin Technology Ltd.
Shenzhen, Guangdong, China
Gates and Inverters
74AUP2G38GN,115
Gates and Inverters 74AUP2G38GN,115
NAND Gate IC 2 Channel Open Drain 8-XSON (1.2x1)

NAND Gate IC 2 Channel Open Drain 8-XSON (1.2x1)

Buy Now Datasheet
Gates and Inverters - 74AUP2G38GN,115 - Quarktwin Technology Ltd.
Shenzhen, Guangdong, China
Gates and Inverters
74AUP2G38GN,115
Gates and Inverters 74AUP2G38GN,115
IC Channel

IC Channel

Buy Now Datasheet
Integrated Circuits (ICs) - Logic - Gates and Inverters - 74AUP2G38GN,115 - Shenzhen Shengyu Electronics Technology Limited
Futian, China
Integrated Circuits (ICs) - Logic - Gates and Inverters
74AUP2G38GN,115
Integrated Circuits (ICs) - Logic - Gates and Inverters 74AUP2G38GN,115
IC GATE NAND 2CH 2-INP 8XSON

IC GATE NAND 2CH 2-INP 8XSON

Supplier's Site

Technical Specifications

  Nexperia B.V. ERSAELECTRONICS PTE. LTD. DigiKey Rochester Electronics Lingto Electronic Limited Quarktwin Technology Ltd. Quarktwin Technology Ltd. Shenzhen Shengyu Electronics Technology Limited
Product Category Logic Gates Logic Gates Logic Gates Logic Gates Logic Gates Logic Gates Logic Gates Logic Gates
Product Number 74AUP2G38GN,115 705-74AUP2G38GN,115 1727-74AUP2G38GN,115TR-ND 74AUP2G38GN,115 74AUP2G38GN,115 74AUP2G38GN,115 74AUP2G38GN,115 74AUP2G38GN,115
Product Name Low-power dual 2-input NAND gate; open drain Dual Logic IC Gates and Inverters Logic - Gates and Inverters Gates and Inverters Gates and Inverters Integrated Circuits (ICs) - Logic - Gates and Inverters
Gate Type NAND NAND NAND AND; NAND NOT; NAND NAND; NAND Gate NAND
Supply Voltage 0.8 - 3.6 0.8V ~ 3.6V 0.8V ~ 3.6V 1.6V ~ 2V (Low), 0.7V ~ 0.9V (High) 3.6V; 0.8V ~ 3.6V 3.6V
Output Type Open Drain Open Drain
Logic Family CMOS AUP CMOS
Propagation Delay 8.5 ns 12.7 ns 12.7 ns
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