Nexperia B.V. Low-power 2-input NAND Schmitt trigger 74AUP1G132GW,125

Description
The 74AUP1G132 is a single 2-input NAND gate with Schmitt-trigger inputs. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. Features and benefits Wide supply voltage range from 0.8 V to 3.6 V CMOS low power dissipation High noise immunity Overvoltage tolerant inputs to 3.6 V Low static power consumption; ICC = 0.9 μA (maximum) Latch-up performance exceeds 100 mA per JESD 78 Class II Low noise overshoot and undershoot < 10 % of VCC IOFF circuitry provides partial Power-down mode operation Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8C (2.7 V to 3.6 V ) ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Multiple package options Specified from -40 °C to +85 °C and -40 °C to +125 °C Applications Wave and pulse shaper Astable multivibrator Monostable multivibrator.
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Description
The 74AUP1G132 is a single 2-input NAND gate with Schmitt-trigger inputs. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. Features and benefits Wide supply voltage range from 0.8 V to 3.6 V CMOS low power dissipation High noise immunity Overvoltage tolerant inputs to 3.6 V Low static power consumption; ICC = 0.9 μA (maximum) Latch-up performance exceeds 100 mA per JESD 78 Class II Low noise overshoot and undershoot < 10 % of VCC IOFF circuitry provides partial Power-down mode operation Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8C (2.7 V to 3.6 V ) ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Multiple package options Specified from -40 °C to +85 °C and -40 °C to +125 °C Applications Wave and pulse shaper Astable multivibrator Monostable multivibrator.
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Suppliers

Company
Product
Description
Supplier Links
Low-power 2-input NAND Schmitt trigger - 74AUP1G132GW,125 - Nexperia B.V.
Nijmegen, Netherlands
Low-power 2-input NAND Schmitt trigger
74AUP1G132GW,125
Low-power 2-input NAND Schmitt trigger 74AUP1G132GW,125
The 74AUP1G132 is a single 2-input NAND gate with Schmitt-trigger inputs. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. Features and benefits Wide supply voltage range from 0.8 V to 3.6 V CMOS low power dissipation High noise immunity Overvoltage tolerant inputs to 3.6 V Low static power consumption; ICC = 0.9 μA (maximum) Latch-up performance exceeds 100 mA per JESD 78 Class II Low noise overshoot and undershoot < 10 % of VCC IOFF circuitry provides partial Power-down mode operation Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8C (2.7 V to 3.6 V ) ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Multiple package options Specified from -40 °C to +85 °C and -40 °C to +125 °C Applications Wave and pulse shaper Astable multivibrator Monostable multivibrator.

The 74AUP1G132 is a single 2-input NAND gate with Schmitt-trigger inputs. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Features and benefits

  • Wide supply voltage range from 0.8 V to 3.6 V
  • CMOS low power dissipation
  • High noise immunity
  • Overvoltage tolerant inputs to 3.6 V
  • Low static power consumption; ICC = 0.9 μA (maximum)
  • Latch-up performance exceeds 100 mA per JESD 78 Class II
  • Low noise overshoot and undershoot < 10 % of VCC
  • IOFF circuitry provides partial Power-down mode operation
  • Complies with JEDEC standards:
    • JESD8-12 (0.8 V to 1.3 V)
    • JESD8-11 (0.9 V to 1.65 V)
    • JESD8-7 (1.65 V to 1.95 V)
    • JESD8-5 (2.3 V to 2.7 V)
    • JESD8C (2.7 V to 3.6 V )
  • ESD protection:
    • HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V
    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
  • Multiple package options
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

Applications

  • Wave and pulse shaper
  • Astable multivibrator
  • Monostable multivibrator.
Supplier's Site Datasheet
Gates and Inverters - 1727-6820-2-ND - DigiKey
Thief River Falls, MN, United States
Gates and Inverters
1727-6820-2-ND
Gates and Inverters 1727-6820-2-ND
NAND Gate IC 1 Channel Schmitt Trigger 5-TSSOP

NAND Gate IC 1 Channel Schmitt Trigger 5-TSSOP

Buy Now Datasheet
Gates and Inverters - 1727-6820-6-ND - DigiKey
Thief River Falls, MN, United States
Gates and Inverters
1727-6820-6-ND
Gates and Inverters 1727-6820-6-ND
NAND Gate IC 1 Channel Schmitt Trigger 5-TSSOP

NAND Gate IC 1 Channel Schmitt Trigger 5-TSSOP

Buy Now Datasheet
Gates and Inverters - 1727-6820-1-ND - DigiKey
Thief River Falls, MN, United States
Gates and Inverters
1727-6820-1-ND
Gates and Inverters 1727-6820-1-ND
NAND Gate IC 1 Channel Schmitt Trigger 5-TSSOP

NAND Gate IC 1 Channel Schmitt Trigger 5-TSSOP

Buy Now Datasheet
Logic - Logic - Gates and Inverters - 74AUP1G132GW,125 - 1007765-74AUP1G132GW,125 - Win Source Electronics
Laguna Hills, CA, United States
Logic - Logic - Gates and Inverters - 74AUP1G132GW,125
1007765-74AUP1G132GW,125
Logic - Logic - Gates and Inverters - 74AUP1G132GW,125 1007765-74AUP1G132GW,125
Manufacturer: Nexperia USA Inc. Win Source Part Number: 1007765-74AUP1G132GW ,125 Packaging: Reel - TR Features: Schmitt Trigger Number of Circuits: 1 Mounting: SMD (SMT) Logic Type: NAND Gate Number of Inputs: 2 Current - Output High, Low: 4mA, 4mA Max Propagation Delay @ V, Max CL: 7.8ns @ 3.3V, 30pF Current - Quiescent (Max): 0.5μA Logic Level - Low: 0.1 V to 0.88 V Logic Level - High: 0.6 V to 2.29 V Categories: Integrated Circuits Status: Active Temperature Range - Operating: -40°C to 125°C Case / Package: 5-TSSOP Dimension: 5-TSSOP, SC-70-5, SOT-353 Supply Voltage - Operating: 0.8 V to 3.6 V Popularity: Medium Fake Threat In the Open Market: 29 pct. Supply and Demand Status: Balance

Manufacturer: Nexperia USA Inc.
Win Source Part Number: 1007765-74AUP1G132GW,125
Packaging: Reel - TR
Features: Schmitt Trigger
Number of Circuits: 1
Mounting: SMD (SMT)
Logic Type: NAND Gate
Number of Inputs: 2
Current - Output High, Low: 4mA, 4mA
Max Propagation Delay @ V, Max CL: 7.8ns @ 3.3V, 30pF
Current - Quiescent (Max): 0.5μA
Logic Level - Low: 0.1 V to 0.88 V
Logic Level - High: 0.6 V to 2.29 V
Categories: Integrated Circuits
Status: Active
Temperature Range - Operating: -40°C to 125°C
Case / Package: 5-TSSOP
Dimension: 5-TSSOP, SC-70-5, SOT-353
Supply Voltage - Operating: 0.8 V to 3.6 V
Popularity: Medium
Fake Threat In the Open Market: 29 pct.
Supply and Demand Status: Balance

Buy Now Datasheet
 - 74AUP1G132GW,125 - Rochester Electronics
Newburyport, MA, United States
NAND Gate, AUP/ULP/V Series, 1-Func, CMOS, PDSO5

NAND Gate, AUP/ULP/V Series, 1-Func, CMOS, PDSO5

Supplier's Site Datasheet
Gates and Inverters - 74AUP1G132GW,125 - Quarktwin Technology Ltd.
Shenzhen, Guangdong, China
Gates and Inverters
74AUP1G132GW,125
Gates and Inverters 74AUP1G132GW,125
NAND Gate IC 1 Channel Schmitt Trigger 5-TSSOP

NAND Gate IC 1 Channel Schmitt Trigger 5-TSSOP

Buy Now Datasheet
Logic - Gates and Inverters - 74AUP1G132GW,125 - Lingto Electronic Limited
Shenzhen, China
Logic - Gates and Inverters
74AUP1G132GW,125
Logic - Gates and Inverters 74AUP1G132GW,125
IC GATE NAND 1CH 2-INP 5TSSOP

IC GATE NAND 1CH 2-INP 5TSSOP

Supplier's Site Datasheet

Technical Specifications

  Nexperia B.V. DigiKey Win Source Electronics Rochester Electronics Quarktwin Technology Ltd. Lingto Electronic Limited
Product Category Logic Gates Logic Gates Logic Gates Logic Gates Logic Gates Logic Gates
Product Number 74AUP1G132GW,125 1727-6820-2-ND 1007765-74AUP1G132GW,125 74AUP1G132GW,125 74AUP1G132GW,125 74AUP1G132GW,125
Product Name Low-power 2-input NAND Schmitt trigger Gates and Inverters Logic - Logic - Gates and Inverters - 74AUP1G132GW,125 Gates and Inverters Logic - Gates and Inverters
Gate Type NAND NAND NOT; NAND; NAND Gate AND; NAND NAND; NAND Gate NOT; NAND
Supply Voltage +4.6 0.8V ~ 3.6V 0.8 V ~ 3.6 V 3.6V; 0.8V ~ 3.6V 0.6V ~ 2.29V (Low), 0.1V ~ 0.88V (High)
Features Schmitt Trigger Schmitt Trigger
Operating Temperature 125 C (257 F) -40 to 125 C (-40 to 257 F) -40 to 125 C (-40 to 257 F) -40 to 125 C (-40 to 257 F)
IC Package Type Other; SOT353-1 SOT353-1 TSSOP; Other; 5-TSSOP, SC-70-5, SOT-353 SOP; SSOP; TSSOP; Other; 5-TSSOP Other; SOT353 SOP; SSOP; TSSOP; Other; 5-TSSOP, SC-70-5, SOT-353
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