Nexperia B.V. 16-bit registered transceiver; 3-state 74ALVCH16952DGG:11

Description
The 74ALVCH16952 consists of two sections, each containing a dual octal non-inverting registered transceiver. Two 8-bit back to back registers store data flowing in both directions between two bidirectional buses. Data applied to the inputs is entered and stored on the rising edge of the clock (nCPAB and nCPBA) provided that the clock enable (nCEAB and nCEBA) is LOW. The data is then present at the output buffers, but is only accessible when the output enable input (nOEAB and nOEBA) is LOW. Data flow from A inputs to B outputs is the same as for B inputs to A outputs. Features and benefits CMOS low-power consumption MULTIBYTE™ flow-through pinout architecture Low inductance, multiple center power and ground pins for minimum noise and ground bounce Direct interface with TTL levels Output drive capability 50 Ω transmission lines at 85 °C Complies with JEDEC standard JESD8-B ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Specified from -40 °C to +85 °C
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16-bit registered transceiver; 3-state - 74ALVCH16952DGG:11 - Nexperia B.V.
Nijmegen, Netherlands
16-bit registered transceiver; 3-state
74ALVCH16952DGG:11
16-bit registered transceiver; 3-state 74ALVCH16952DGG:11
The 74ALVCH16952 consists of two sections, each containing a dual octal non-inverting registered transceiver. Two 8-bit back to back registers store data flowing in both directions between two bidirectional buses. Data applied to the inputs is entered and stored on the rising edge of the clock (nCPAB and nCPBA) provided that the clock enable (nCEAB and nCEBA) is LOW. The data is then present at the output buffers, but is only accessible when the output enable input (nOEAB and nOEBA) is LOW. Data flow from A inputs to B outputs is the same as for B inputs to A outputs. Features and benefits CMOS low-power consumption MULTIBYTE™ flow-through pinout architecture Low inductance, multiple center power and ground pins for minimum noise and ground bounce Direct interface with TTL levels Output drive capability 50 Ω transmission lines at 85 °C Complies with JEDEC standard JESD8-B ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Specified from -40 °C to +85 °C

The 74ALVCH16952 consists of two sections, each containing a dual octal non-inverting registered transceiver. Two 8-bit back to back registers store data flowing in both directions between two bidirectional buses. Data applied to the inputs is entered and stored on the rising edge of the clock (nCPAB and nCPBA) provided that the clock enable (nCEAB and nCEBA) is LOW. The data is then present at the output buffers, but is only accessible when the output enable input (nOEAB and nOEBA) is LOW. Data flow from A inputs to B outputs is the same as for B inputs to A outputs.

Features and benefits

  • CMOS low-power consumption
  • MULTIBYTE™ flow-through pinout architecture
  • Low inductance, multiple center power and ground pins for minimum noise and ground bounce
  • Direct interface with TTL levels
  • Output drive capability 50 Ω transmission lines at 85 °C
  • Complies with JEDEC standard JESD8-B
  • ESD protection:
    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
  • Specified from -40 °C to +85 °C
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Technical Specifications

  Nexperia B.V.
Product Category RF Transmitters
Product Number 74ALVCH16952DGG:11
Product Name 16-bit registered transceiver; 3-state
Package Type SOT364-1
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