TThe 74ALVCH16543 is a 16-bit registered transceiver with bus hold inputs and 3-state outputs. The device can be used as two 8-bit transceivers or one 16-bit transceiver.
Data flow in each direction is controlled by intput enable (nEAB and nEBA), latch enable (nLEAB and nLEBA), and output enable (nOEAB and nOEBA) inputs. For A to B data flow, the device operates in the transparen mode when (nEAB) and (nLEAB) are LOW. A subsequent LOW-to-HIGH transition of the nLEAB input latches the data and the outputs no longer change with the inputs. A HIGH on either nEAB or nOEAB causes the outputs to assume a high-impedance OFF-state.
Control of data flow from B to A is similar, but using the nEBA, nLEBA, and nOEBA inputs. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
Features and benefits
Wide supply voltage range from 1.65 V to 3.6 V
CMOS low power dissipation
Direct interface with TTL levels
MULTIBYTE™ flow-through standard pin-out architecture
Back-to-back registers for storage
Output drive capability 50 Ω transmission lines at 85 °C
All data inputs have bushold
Low inductance multiple VCC and GND pins for minimize noise and ground bounce
Current drive ±24 mA at VCC = 3.0 V.
3-state non-inverting outputs for bus oriented applications
Complies with JEDEC standards:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8C (2.7 V to 3.6 V)
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
TThe 74ALVCH16543 is a 16-bit registered transceiver with bus hold inputs and 3-state outputs. The device can be used as two 8-bit transceivers or one 16-bit transceiver.
Data flow in each direction is controlled by intput enable (nEAB and nEBA), latch enable (nLEAB and nLEBA), and output enable (nOEAB and nOEBA) inputs. For A to B data flow, the device operates in the transparen mode when (nEAB) and (nLEAB) are LOW. A subsequent LOW-to-HIGH transition of the nLEAB input latches the data and the outputs no longer change with the inputs. A HIGH on either nEAB or nOEAB causes the outputs to assume a high-impedance OFF-state.
Control of data flow from B to A is similar, but using the nEBA, nLEBA, and nOEBA inputs. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
Features and benefits
- Wide supply voltage range from 1.65 V to 3.6 V
- CMOS low power dissipation
- Direct interface with TTL levels
- MULTIBYTE™ flow-through standard pin-out architecture
- Back-to-back registers for storage
- Output drive capability 50 Ω transmission lines at 85 °C
- All data inputs have bushold
- Low inductance multiple VCC and GND pins for minimize noise and ground bounce
- Current drive ±24 mA at VCC = 3.0 V.
- 3-state non-inverting outputs for bus oriented applications
- Complies with JEDEC standards:
- JESD8-7 (1.65 V to 1.95 V)
- JESD8-5 (2.3 V to 2.7 V)
- JESD8C (2.7 V to 3.6 V)
- ESD protection:
- HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
- CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
- Specified from -40 °C to +85 °C and from -40 °C to +125 °C
