The ZL40231 is a low additive jitter, low power 3 x 10 LVPECL/HCSL/LVDS fanout buffer.
Two inputs can accept signal in differential (LVPECL, SSTL, LVDS, HSTL, CML ) or single ended (LVPECL or LVCMOS) format and the third input can accept a single ended signal or it can be used to build a crystal oscillator by connecting an external crystal resonator between its XIN and XOUT pins.
The ZL40231 has ten LVPECL/HCSL/LVDS outputs which can be powered from 3.3V or 2.5V supply. Each output bank (A and B) can be independently set to be LVPECL, LVDS, HCSL or Hi-Z via control OUTA/B_TYPE_SEL0/1 pins.
The control inputs: OUTA/B_TYPE_SEL0/1 and IN_SEL0/1 have low input threshold voltage so they can be driven from a device with low I/O voltage (down to 1.2V).
Additional Features
3 to 1 input Multiplexer: Two inputs accept any differential (LVPECL, HCSL, LVDS, SSTL, CML, LVCMOS) or a single ended signal and the third input accepts a crystal or a single ended signal
Ten differential LVPECL/LVDS/HCSL outputs
One LVCMOS output
Ultra-low additive jitter: 24fs (integration band: 12kHz to 20MHz at 625MHz clock frequency)
Supports clock frequencies from 0 to 1.6GHz
Supports 2.5V or 3.3V power supplies on LVPECL,LVDS or HCSL outputs
Supports 1.5V, 1.8V, 2.5V or 3.3V on LVCMOS outputs
Embedded Low Drop Out (LDO) Voltage regulator provides superior Power Supply Noise Rejection
Maximum output to output skew of 40ps
Device controlled via control pins
The ZL40231 is a low additive jitter, low power 3 x 10 LVPECL/HCSL/LVDS fanout buffer.
Two inputs can accept signal in differential (LVPECL, SSTL, LVDS, HSTL, CML ) or single ended (LVPECL or LVCMOS) format and the third input can accept a single ended signal or it can be used to build a crystal oscillator by connecting an external crystal resonator between its XIN and XOUT pins.
The ZL40231 has ten LVPECL/HCSL/LVDS outputs which can be powered from 3.3V or 2.5V supply. Each output bank (A and B) can be independently set to be LVPECL, LVDS, HCSL or Hi-Z via control OUTA/B_TYPE_SEL0/1 pins.
The control inputs: OUTA/B_TYPE_SEL0/1 and IN_SEL0/1 have low input threshold voltage so they can be driven from a device with low I/O voltage (down to 1.2V).
Additional Features
- 3 to 1 input Multiplexer: Two inputs accept any differential (LVPECL, HCSL, LVDS, SSTL, CML, LVCMOS) or a single ended signal and the third input accepts a crystal or a single ended signal
- Ten differential LVPECL/LVDS/HCSL outputs
- One LVCMOS output
- Ultra-low additive jitter: 24fs (integration band: 12kHz to 20MHz at 625MHz clock frequency)
- Supports clock frequencies from 0 to 1.6GHz
- Supports 2.5V or 3.3V power supplies on LVPECL,LVDS or HCSL outputs
- Supports 1.5V, 1.8V, 2.5V or 3.3V on LVCMOS outputs
- Embedded Low Drop Out (LDO) Voltage regulator provides superior Power Supply Noise Rejection
- Maximum output to output skew of 40ps
- Device controlled via control pins
